Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1 | /* |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 2 | * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
| 5 | */ |
| 6 | |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 7 | #include <assert.h> |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 8 | #include <errno.h> |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 9 | #include <stdint.h> |
Antonio Nino Diaz | 00086e3 | 2018-08-16 16:46:06 +0100 | [diff] [blame] | 10 | #include <stdio.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | |
| 12 | #include <libfdt.h> |
| 13 | |
Yann Gautier | 57e282b | 2019-01-07 11:17:24 +0100 | [diff] [blame] | 14 | #include <platform_def.h> |
| 15 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 16 | #include <arch.h> |
| 17 | #include <arch_helpers.h> |
| 18 | #include <common/debug.h> |
| 19 | #include <drivers/delay_timer.h> |
| 20 | #include <drivers/generic_delay_timer.h> |
Yann Gautier | 4d42947 | 2019-02-14 11:15:20 +0100 | [diff] [blame] | 21 | #include <drivers/st/stm32mp_clkfunc.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 22 | #include <drivers/st/stm32mp1_clk.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 23 | #include <drivers/st/stm32mp1_rcc.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 24 | #include <dt-bindings/clock/stm32mp1-clksrc.h> |
| 25 | #include <lib/mmio.h> |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 26 | #include <lib/spinlock.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 27 | #include <lib/utils_def.h> |
| 28 | #include <plat/common/platform.h> |
| 29 | |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 30 | #define MAX_HSI_HZ 64000000 |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 31 | #define USB_PHY_48_MHZ 48000000 |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 32 | |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 33 | #define TIMEOUT_US_200MS U(200000) |
| 34 | #define TIMEOUT_US_1S U(1000000) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 35 | |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 36 | #define PLLRDY_TIMEOUT TIMEOUT_US_200MS |
| 37 | #define CLKSRC_TIMEOUT TIMEOUT_US_200MS |
| 38 | #define CLKDIV_TIMEOUT TIMEOUT_US_200MS |
| 39 | #define HSIDIV_TIMEOUT TIMEOUT_US_200MS |
| 40 | #define OSCRDY_TIMEOUT TIMEOUT_US_1S |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 41 | |
Yann Gautier | 5f2e874 | 2019-05-17 15:57:56 +0200 | [diff] [blame] | 42 | const char *stm32mp_osc_node_label[NB_OSC] = { |
| 43 | [_LSI] = "clk-lsi", |
| 44 | [_LSE] = "clk-lse", |
| 45 | [_HSI] = "clk-hsi", |
| 46 | [_HSE] = "clk-hse", |
| 47 | [_CSI] = "clk-csi", |
| 48 | [_I2S_CKIN] = "i2s_ckin", |
| 49 | }; |
| 50 | |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 51 | enum stm32mp1_parent_id { |
| 52 | /* Oscillators are defined in enum stm32mp_osc_id */ |
| 53 | |
| 54 | /* Other parent source */ |
| 55 | _HSI_KER = NB_OSC, |
| 56 | _HSE_KER, |
| 57 | _HSE_KER_DIV2, |
| 58 | _CSI_KER, |
| 59 | _PLL1_P, |
| 60 | _PLL1_Q, |
| 61 | _PLL1_R, |
| 62 | _PLL2_P, |
| 63 | _PLL2_Q, |
| 64 | _PLL2_R, |
| 65 | _PLL3_P, |
| 66 | _PLL3_Q, |
| 67 | _PLL3_R, |
| 68 | _PLL4_P, |
| 69 | _PLL4_Q, |
| 70 | _PLL4_R, |
| 71 | _ACLK, |
| 72 | _PCLK1, |
| 73 | _PCLK2, |
| 74 | _PCLK3, |
| 75 | _PCLK4, |
| 76 | _PCLK5, |
| 77 | _HCLK6, |
| 78 | _HCLK2, |
| 79 | _CK_PER, |
| 80 | _CK_MPU, |
Yann Gautier | ed34232 | 2019-02-15 17:33:27 +0100 | [diff] [blame] | 81 | _CK_MCU, |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 82 | _USB_PHY_48, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 83 | _PARENT_NB, |
| 84 | _UNKNOWN_ID = 0xff, |
| 85 | }; |
| 86 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 87 | /* Lists only the parent clock we are interested in */ |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 88 | enum stm32mp1_parent_sel { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 89 | _I2C12_SEL, |
| 90 | _I2C35_SEL, |
| 91 | _STGEN_SEL, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 92 | _I2C46_SEL, |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 93 | _SPI6_SEL, |
Yann Gautier | 9d8bbcd | 2019-05-07 18:49:33 +0200 | [diff] [blame] | 94 | _UART1_SEL, |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 95 | _RNG1_SEL, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 96 | _UART6_SEL, |
| 97 | _UART24_SEL, |
| 98 | _UART35_SEL, |
| 99 | _UART78_SEL, |
| 100 | _SDMMC12_SEL, |
| 101 | _SDMMC3_SEL, |
| 102 | _QSPI_SEL, |
| 103 | _FMC_SEL, |
Yann Gautier | 9d8bbcd | 2019-05-07 18:49:33 +0200 | [diff] [blame] | 104 | _AXIS_SEL, |
| 105 | _MCUS_SEL, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 106 | _USBPHY_SEL, |
| 107 | _USBO_SEL, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 108 | _PARENT_SEL_NB, |
| 109 | _UNKNOWN_SEL = 0xff, |
| 110 | }; |
| 111 | |
| 112 | enum stm32mp1_pll_id { |
| 113 | _PLL1, |
| 114 | _PLL2, |
| 115 | _PLL3, |
| 116 | _PLL4, |
| 117 | _PLL_NB |
| 118 | }; |
| 119 | |
| 120 | enum stm32mp1_div_id { |
| 121 | _DIV_P, |
| 122 | _DIV_Q, |
| 123 | _DIV_R, |
| 124 | _DIV_NB, |
| 125 | }; |
| 126 | |
| 127 | enum stm32mp1_clksrc_id { |
| 128 | CLKSRC_MPU, |
| 129 | CLKSRC_AXI, |
Yann Gautier | ed34232 | 2019-02-15 17:33:27 +0100 | [diff] [blame] | 130 | CLKSRC_MCU, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 131 | CLKSRC_PLL12, |
| 132 | CLKSRC_PLL3, |
| 133 | CLKSRC_PLL4, |
| 134 | CLKSRC_RTC, |
| 135 | CLKSRC_MCO1, |
| 136 | CLKSRC_MCO2, |
| 137 | CLKSRC_NB |
| 138 | }; |
| 139 | |
| 140 | enum stm32mp1_clkdiv_id { |
| 141 | CLKDIV_MPU, |
| 142 | CLKDIV_AXI, |
Yann Gautier | ed34232 | 2019-02-15 17:33:27 +0100 | [diff] [blame] | 143 | CLKDIV_MCU, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 144 | CLKDIV_APB1, |
| 145 | CLKDIV_APB2, |
| 146 | CLKDIV_APB3, |
| 147 | CLKDIV_APB4, |
| 148 | CLKDIV_APB5, |
| 149 | CLKDIV_RTC, |
| 150 | CLKDIV_MCO1, |
| 151 | CLKDIV_MCO2, |
| 152 | CLKDIV_NB |
| 153 | }; |
| 154 | |
| 155 | enum stm32mp1_pllcfg { |
| 156 | PLLCFG_M, |
| 157 | PLLCFG_N, |
| 158 | PLLCFG_P, |
| 159 | PLLCFG_Q, |
| 160 | PLLCFG_R, |
| 161 | PLLCFG_O, |
| 162 | PLLCFG_NB |
| 163 | }; |
| 164 | |
| 165 | enum stm32mp1_pllcsg { |
| 166 | PLLCSG_MOD_PER, |
| 167 | PLLCSG_INC_STEP, |
| 168 | PLLCSG_SSCG_MODE, |
| 169 | PLLCSG_NB |
| 170 | }; |
| 171 | |
| 172 | enum stm32mp1_plltype { |
| 173 | PLL_800, |
| 174 | PLL_1600, |
| 175 | PLL_TYPE_NB |
| 176 | }; |
| 177 | |
| 178 | struct stm32mp1_pll { |
| 179 | uint8_t refclk_min; |
| 180 | uint8_t refclk_max; |
| 181 | uint8_t divn_max; |
| 182 | }; |
| 183 | |
| 184 | struct stm32mp1_clk_gate { |
| 185 | uint16_t offset; |
| 186 | uint8_t bit; |
| 187 | uint8_t index; |
| 188 | uint8_t set_clr; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 189 | uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ |
| 190 | uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 191 | }; |
| 192 | |
| 193 | struct stm32mp1_clk_sel { |
| 194 | uint16_t offset; |
| 195 | uint8_t src; |
| 196 | uint8_t msk; |
| 197 | uint8_t nb_parent; |
| 198 | const uint8_t *parent; |
| 199 | }; |
| 200 | |
| 201 | #define REFCLK_SIZE 4 |
| 202 | struct stm32mp1_clk_pll { |
| 203 | enum stm32mp1_plltype plltype; |
| 204 | uint16_t rckxselr; |
| 205 | uint16_t pllxcfgr1; |
| 206 | uint16_t pllxcfgr2; |
| 207 | uint16_t pllxfracr; |
| 208 | uint16_t pllxcr; |
| 209 | uint16_t pllxcsgr; |
| 210 | enum stm32mp_osc_id refclk[REFCLK_SIZE]; |
| 211 | }; |
| 212 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 213 | /* Clocks with selectable source and non set/clr register access */ |
| 214 | #define _CLK_SELEC(off, b, idx, s) \ |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 215 | { \ |
| 216 | .offset = (off), \ |
| 217 | .bit = (b), \ |
| 218 | .index = (idx), \ |
| 219 | .set_clr = 0, \ |
| 220 | .sel = (s), \ |
| 221 | .fixed = _UNKNOWN_ID, \ |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 222 | } |
| 223 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 224 | /* Clocks with fixed source and non set/clr register access */ |
| 225 | #define _CLK_FIXED(off, b, idx, f) \ |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 226 | { \ |
| 227 | .offset = (off), \ |
| 228 | .bit = (b), \ |
| 229 | .index = (idx), \ |
| 230 | .set_clr = 0, \ |
| 231 | .sel = _UNKNOWN_SEL, \ |
| 232 | .fixed = (f), \ |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 233 | } |
| 234 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 235 | /* Clocks with selectable source and set/clr register access */ |
| 236 | #define _CLK_SC_SELEC(off, b, idx, s) \ |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 237 | { \ |
| 238 | .offset = (off), \ |
| 239 | .bit = (b), \ |
| 240 | .index = (idx), \ |
| 241 | .set_clr = 1, \ |
| 242 | .sel = (s), \ |
| 243 | .fixed = _UNKNOWN_ID, \ |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 244 | } |
| 245 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 246 | /* Clocks with fixed source and set/clr register access */ |
| 247 | #define _CLK_SC_FIXED(off, b, idx, f) \ |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 248 | { \ |
| 249 | .offset = (off), \ |
| 250 | .bit = (b), \ |
| 251 | .index = (idx), \ |
| 252 | .set_clr = 1, \ |
| 253 | .sel = _UNKNOWN_SEL, \ |
| 254 | .fixed = (f), \ |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 255 | } |
| 256 | |
Yann Gautier | 9d8bbcd | 2019-05-07 18:49:33 +0200 | [diff] [blame] | 257 | #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ |
| 258 | [_ ## _label ## _SEL] = { \ |
| 259 | .offset = _rcc_selr, \ |
| 260 | .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ |
| 261 | .msk = _rcc_selr ## _ ## _label ## SRC_MASK, \ |
| 262 | .parent = (_parents), \ |
| 263 | .nb_parent = ARRAY_SIZE(_parents) \ |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 264 | } |
| 265 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 266 | #define _CLK_PLL(idx, type, off1, off2, off3, \ |
| 267 | off4, off5, off6, \ |
| 268 | p1, p2, p3, p4) \ |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 269 | [(idx)] = { \ |
| 270 | .plltype = (type), \ |
| 271 | .rckxselr = (off1), \ |
| 272 | .pllxcfgr1 = (off2), \ |
| 273 | .pllxcfgr2 = (off3), \ |
| 274 | .pllxfracr = (off4), \ |
| 275 | .pllxcr = (off5), \ |
| 276 | .pllxcsgr = (off6), \ |
| 277 | .refclk[0] = (p1), \ |
| 278 | .refclk[1] = (p2), \ |
| 279 | .refclk[2] = (p3), \ |
| 280 | .refclk[3] = (p4), \ |
| 281 | } |
| 282 | |
| 283 | static const uint8_t stm32mp1_clks[][2] = { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 284 | { CK_PER, _CK_PER }, |
| 285 | { CK_MPU, _CK_MPU }, |
| 286 | { CK_AXI, _ACLK }, |
Yann Gautier | ed34232 | 2019-02-15 17:33:27 +0100 | [diff] [blame] | 287 | { CK_MCU, _CK_MCU }, |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 288 | { CK_HSE, _HSE }, |
| 289 | { CK_CSI, _CSI }, |
| 290 | { CK_LSI, _LSI }, |
| 291 | { CK_LSE, _LSE }, |
| 292 | { CK_HSI, _HSI }, |
| 293 | { CK_HSE_DIV2, _HSE_KER_DIV2 }, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 294 | }; |
| 295 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 296 | #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) |
| 297 | |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 298 | static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 299 | _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK), |
| 300 | _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK), |
| 301 | _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK), |
| 302 | _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK), |
| 303 | _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), |
| 304 | _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), |
| 305 | _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), |
| 306 | _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), |
| 307 | _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK), |
| 308 | _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), |
| 309 | _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), |
| 310 | |
| 311 | _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), |
| 312 | _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), |
| 313 | _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), |
| 314 | _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), |
| 315 | _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), |
| 316 | _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), |
| 317 | _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), |
| 318 | _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), |
| 319 | _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), |
| 320 | _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), |
| 321 | _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), |
| 322 | |
| 323 | _CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), |
| 324 | _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), |
| 325 | |
| 326 | _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), |
| 327 | _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), |
| 328 | _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), |
| 329 | |
| 330 | _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), |
| 331 | _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), |
| 332 | _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), |
Yann Gautier | 9d8bbcd | 2019-05-07 18:49:33 +0200 | [diff] [blame] | 333 | _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 334 | _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), |
| 335 | _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), |
| 336 | _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), |
| 337 | _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), |
| 338 | _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), |
| 339 | _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), |
| 340 | _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), |
| 341 | |
| 342 | _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), |
| 343 | _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), |
| 344 | |
| 345 | _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), |
| 346 | _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), |
| 347 | _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), |
| 348 | _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), |
| 349 | _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), |
| 350 | _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), |
| 351 | _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), |
| 352 | _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), |
| 353 | _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), |
| 354 | _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), |
| 355 | _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), |
| 356 | |
| 357 | _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), |
| 358 | _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), |
| 359 | _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), |
| 360 | _CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), |
| 361 | _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), |
| 362 | |
| 363 | _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), |
| 364 | _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), |
| 365 | _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), |
| 366 | _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), |
| 367 | _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), |
| 368 | |
| 369 | _CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), |
| 370 | }; |
| 371 | |
| 372 | static const uint8_t i2c12_parents[] = { |
| 373 | _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER |
| 374 | }; |
| 375 | |
| 376 | static const uint8_t i2c35_parents[] = { |
| 377 | _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER |
| 378 | }; |
| 379 | |
| 380 | static const uint8_t stgen_parents[] = { |
| 381 | _HSI_KER, _HSE_KER |
| 382 | }; |
| 383 | |
| 384 | static const uint8_t i2c46_parents[] = { |
| 385 | _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER |
| 386 | }; |
| 387 | |
| 388 | static const uint8_t spi6_parents[] = { |
| 389 | _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q |
| 390 | }; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 391 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 392 | static const uint8_t usart1_parents[] = { |
| 393 | _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER |
| 394 | }; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 395 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 396 | static const uint8_t rng1_parents[] = { |
| 397 | _CSI, _PLL4_R, _LSE, _LSI |
| 398 | }; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 399 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 400 | static const uint8_t uart6_parents[] = { |
| 401 | _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER |
| 402 | }; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 403 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 404 | static const uint8_t uart234578_parents[] = { |
| 405 | _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER |
| 406 | }; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 407 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 408 | static const uint8_t sdmmc12_parents[] = { |
| 409 | _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER |
| 410 | }; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 411 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 412 | static const uint8_t sdmmc3_parents[] = { |
| 413 | _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER |
| 414 | }; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 415 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 416 | static const uint8_t qspi_parents[] = { |
| 417 | _ACLK, _PLL3_R, _PLL4_P, _CK_PER |
| 418 | }; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 419 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 420 | static const uint8_t fmc_parents[] = { |
| 421 | _ACLK, _PLL3_R, _PLL4_P, _CK_PER |
| 422 | }; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 423 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 424 | static const uint8_t ass_parents[] = { |
| 425 | _HSI, _HSE, _PLL2 |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 426 | }; |
| 427 | |
Yann Gautier | ed34232 | 2019-02-15 17:33:27 +0100 | [diff] [blame] | 428 | static const uint8_t mss_parents[] = { |
| 429 | _HSI, _HSE, _CSI, _PLL3 |
| 430 | }; |
| 431 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 432 | static const uint8_t usbphy_parents[] = { |
| 433 | _HSE_KER, _PLL4_R, _HSE_KER_DIV2 |
| 434 | }; |
| 435 | |
| 436 | static const uint8_t usbo_parents[] = { |
| 437 | _PLL4_R, _USB_PHY_48 |
| 438 | }; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 439 | |
| 440 | static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { |
Yann Gautier | 9d8bbcd | 2019-05-07 18:49:33 +0200 | [diff] [blame] | 441 | _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), |
| 442 | _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), |
| 443 | _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), |
| 444 | _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), |
| 445 | _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), |
| 446 | _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), |
| 447 | _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), |
| 448 | _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), |
| 449 | _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), |
| 450 | _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), |
| 451 | _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), |
| 452 | _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), |
| 453 | _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), |
| 454 | _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), |
| 455 | _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), |
| 456 | _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, ass_parents), |
| 457 | _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mss_parents), |
| 458 | _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), |
| 459 | _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 460 | }; |
| 461 | |
| 462 | /* Define characteristic of PLL according type */ |
| 463 | #define DIVN_MIN 24 |
| 464 | static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { |
| 465 | [PLL_800] = { |
| 466 | .refclk_min = 4, |
| 467 | .refclk_max = 16, |
| 468 | .divn_max = 99, |
| 469 | }, |
| 470 | [PLL_1600] = { |
| 471 | .refclk_min = 8, |
| 472 | .refclk_max = 16, |
| 473 | .divn_max = 199, |
| 474 | }, |
| 475 | }; |
| 476 | |
| 477 | /* PLLNCFGR2 register divider by output */ |
| 478 | static const uint8_t pllncfgr2[_DIV_NB] = { |
| 479 | [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, |
| 480 | [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 481 | [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 482 | }; |
| 483 | |
| 484 | static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 485 | _CLK_PLL(_PLL1, PLL_1600, |
| 486 | RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, |
| 487 | RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, |
| 488 | _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), |
| 489 | _CLK_PLL(_PLL2, PLL_1600, |
| 490 | RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, |
| 491 | RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, |
| 492 | _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), |
| 493 | _CLK_PLL(_PLL3, PLL_800, |
| 494 | RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, |
| 495 | RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, |
| 496 | _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), |
| 497 | _CLK_PLL(_PLL4, PLL_800, |
| 498 | RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, |
| 499 | RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, |
| 500 | _HSI, _HSE, _CSI, _I2S_CKIN), |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 501 | }; |
| 502 | |
| 503 | /* Prescaler table lookups for clock computation */ |
Yann Gautier | ed34232 | 2019-02-15 17:33:27 +0100 | [diff] [blame] | 504 | /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ |
| 505 | static const uint8_t stm32mp1_mcu_div[16] = { |
| 506 | 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 |
| 507 | }; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 508 | |
| 509 | /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ |
| 510 | #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div |
| 511 | #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div |
| 512 | static const uint8_t stm32mp1_mpu_apbx_div[8] = { |
| 513 | 0, 1, 2, 3, 4, 4, 4, 4 |
| 514 | }; |
| 515 | |
| 516 | /* div = /1 /2 /3 /4 */ |
| 517 | static const uint8_t stm32mp1_axi_div[8] = { |
| 518 | 1, 2, 3, 4, 4, 4, 4, 4 |
| 519 | }; |
| 520 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 521 | /* RCC clock device driver private */ |
| 522 | static unsigned long stm32mp1_osc[NB_OSC]; |
| 523 | static struct spinlock reg_lock; |
| 524 | static unsigned int gate_refcounts[NB_GATES]; |
| 525 | static struct spinlock refcount_lock; |
| 526 | |
| 527 | static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) |
| 528 | { |
| 529 | return &stm32mp1_clk_gate[idx]; |
| 530 | } |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 531 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 532 | static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) |
| 533 | { |
| 534 | return &stm32mp1_clk_sel[idx]; |
| 535 | } |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 536 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 537 | static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) |
| 538 | { |
| 539 | return &stm32mp1_clk_pll[idx]; |
| 540 | } |
| 541 | |
| 542 | static int stm32mp1_lock_available(void) |
| 543 | { |
| 544 | /* The spinlocks are used only when MMU is enabled */ |
| 545 | return (read_sctlr() & SCTLR_M_BIT) && (read_sctlr() & SCTLR_C_BIT); |
| 546 | } |
| 547 | |
| 548 | static void stm32mp1_clk_lock(struct spinlock *lock) |
| 549 | { |
| 550 | if (stm32mp1_lock_available() == 0U) { |
| 551 | return; |
| 552 | } |
| 553 | |
| 554 | /* Assume interrupts are masked */ |
| 555 | spin_lock(lock); |
| 556 | } |
| 557 | |
| 558 | static void stm32mp1_clk_unlock(struct spinlock *lock) |
| 559 | { |
| 560 | if (stm32mp1_lock_available() == 0U) { |
| 561 | return; |
| 562 | } |
| 563 | |
| 564 | spin_unlock(lock); |
| 565 | } |
| 566 | |
| 567 | bool stm32mp1_rcc_is_secure(void) |
| 568 | { |
| 569 | uintptr_t rcc_base = stm32mp_rcc_base(); |
| 570 | |
| 571 | return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_TZEN) != 0; |
| 572 | } |
| 573 | |
Yann Gautier | ed34232 | 2019-02-15 17:33:27 +0100 | [diff] [blame] | 574 | bool stm32mp1_rcc_is_mckprot(void) |
| 575 | { |
| 576 | uintptr_t rcc_base = stm32mp_rcc_base(); |
| 577 | |
| 578 | return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_MCKPROT) != 0; |
| 579 | } |
| 580 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 581 | void stm32mp1_clk_rcc_regs_lock(void) |
| 582 | { |
| 583 | stm32mp1_clk_lock(®_lock); |
| 584 | } |
| 585 | |
| 586 | void stm32mp1_clk_rcc_regs_unlock(void) |
| 587 | { |
| 588 | stm32mp1_clk_unlock(®_lock); |
| 589 | } |
| 590 | |
| 591 | static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 592 | { |
| 593 | if (idx >= NB_OSC) { |
| 594 | return 0; |
| 595 | } |
| 596 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 597 | return stm32mp1_osc[idx]; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 598 | } |
| 599 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 600 | static int stm32mp1_clk_get_gated_id(unsigned long id) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 601 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 602 | unsigned int i; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 603 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 604 | for (i = 0U; i < NB_GATES; i++) { |
| 605 | if (gate_ref(i)->index == id) { |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 606 | return i; |
| 607 | } |
| 608 | } |
| 609 | |
| 610 | ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id); |
| 611 | |
| 612 | return -EINVAL; |
| 613 | } |
| 614 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 615 | static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 616 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 617 | return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 618 | } |
| 619 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 620 | static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 621 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 622 | return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 623 | } |
| 624 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 625 | static int stm32mp1_clk_get_parent(unsigned long id) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 626 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 627 | const struct stm32mp1_clk_sel *sel; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 628 | uint32_t j, p_sel; |
| 629 | int i; |
| 630 | enum stm32mp1_parent_id p; |
| 631 | enum stm32mp1_parent_sel s; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 632 | uintptr_t rcc_base = stm32mp_rcc_base(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 633 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 634 | for (j = 0U; j < ARRAY_SIZE(stm32mp1_clks); j++) { |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 635 | if (stm32mp1_clks[j][0] == id) { |
| 636 | return (int)stm32mp1_clks[j][1]; |
| 637 | } |
| 638 | } |
| 639 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 640 | i = stm32mp1_clk_get_gated_id(id); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 641 | if (i < 0) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 642 | panic(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 643 | } |
| 644 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 645 | p = stm32mp1_clk_get_fixed_parent(i); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 646 | if (p < _PARENT_NB) { |
| 647 | return (int)p; |
| 648 | } |
| 649 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 650 | s = stm32mp1_clk_get_sel(i); |
| 651 | if (s == _UNKNOWN_SEL) { |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 652 | return -EINVAL; |
| 653 | } |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 654 | if (s >= _PARENT_SEL_NB) { |
| 655 | panic(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 656 | } |
| 657 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 658 | sel = clk_sel_ref(s); |
Yann Gautier | 9d8bbcd | 2019-05-07 18:49:33 +0200 | [diff] [blame] | 659 | p_sel = (mmio_read_32(rcc_base + sel->offset) & sel->msk) >> sel->src; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 660 | if (p_sel < sel->nb_parent) { |
| 661 | return (int)sel->parent[p_sel]; |
| 662 | } |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 663 | |
| 664 | return -EINVAL; |
| 665 | } |
| 666 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 667 | static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 668 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 669 | uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); |
| 670 | uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 671 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 672 | return stm32mp1_clk_get_fixed(pll->refclk[src]); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 673 | } |
| 674 | |
| 675 | /* |
| 676 | * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL |
| 677 | * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) |
| 678 | * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) |
| 679 | * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) |
| 680 | */ |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 681 | static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 682 | { |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 683 | unsigned long refclk, fvco; |
| 684 | uint32_t cfgr1, fracr, divm, divn; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 685 | uintptr_t rcc_base = stm32mp_rcc_base(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 686 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 687 | cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); |
| 688 | fracr = mmio_read_32(rcc_base + pll->pllxfracr); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 689 | |
| 690 | divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; |
| 691 | divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; |
| 692 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 693 | refclk = stm32mp1_pll_get_fref(pll); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 694 | |
| 695 | /* |
| 696 | * With FRACV : |
| 697 | * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) |
| 698 | * Without FRACV |
| 699 | * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) |
| 700 | */ |
| 701 | if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 702 | uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> |
| 703 | RCC_PLLNFRACR_FRACV_SHIFT; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 704 | unsigned long long numerator, denominator; |
| 705 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 706 | numerator = (((unsigned long long)divn + 1U) << 13) + fracv; |
| 707 | numerator = refclk * numerator; |
| 708 | denominator = ((unsigned long long)divm + 1U) << 13; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 709 | fvco = (unsigned long)(numerator / denominator); |
| 710 | } else { |
| 711 | fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); |
| 712 | } |
| 713 | |
| 714 | return fvco; |
| 715 | } |
| 716 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 717 | static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 718 | enum stm32mp1_div_id div_id) |
| 719 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 720 | const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 721 | unsigned long dfout; |
| 722 | uint32_t cfgr2, divy; |
| 723 | |
| 724 | if (div_id >= _DIV_NB) { |
| 725 | return 0; |
| 726 | } |
| 727 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 728 | cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 729 | divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; |
| 730 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 731 | dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 732 | |
| 733 | return dfout; |
| 734 | } |
| 735 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 736 | static unsigned long get_clock_rate(int p) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 737 | { |
| 738 | uint32_t reg, clkdiv; |
| 739 | unsigned long clock = 0; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 740 | uintptr_t rcc_base = stm32mp_rcc_base(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 741 | |
| 742 | switch (p) { |
| 743 | case _CK_MPU: |
| 744 | /* MPU sub system */ |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 745 | reg = mmio_read_32(rcc_base + RCC_MPCKSELR); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 746 | switch (reg & RCC_SELR_SRC_MASK) { |
| 747 | case RCC_MPCKSELR_HSI: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 748 | clock = stm32mp1_clk_get_fixed(_HSI); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 749 | break; |
| 750 | case RCC_MPCKSELR_HSE: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 751 | clock = stm32mp1_clk_get_fixed(_HSE); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 752 | break; |
| 753 | case RCC_MPCKSELR_PLL: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 754 | clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 755 | break; |
| 756 | case RCC_MPCKSELR_PLL_MPUDIV: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 757 | clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 758 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 759 | reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 760 | clkdiv = reg & RCC_MPUDIV_MASK; |
| 761 | if (clkdiv != 0U) { |
| 762 | clock /= stm32mp1_mpu_div[clkdiv]; |
| 763 | } |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 764 | break; |
| 765 | default: |
| 766 | break; |
| 767 | } |
| 768 | break; |
| 769 | /* AXI sub system */ |
| 770 | case _ACLK: |
| 771 | case _HCLK2: |
| 772 | case _HCLK6: |
| 773 | case _PCLK4: |
| 774 | case _PCLK5: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 775 | reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 776 | switch (reg & RCC_SELR_SRC_MASK) { |
| 777 | case RCC_ASSCKSELR_HSI: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 778 | clock = stm32mp1_clk_get_fixed(_HSI); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 779 | break; |
| 780 | case RCC_ASSCKSELR_HSE: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 781 | clock = stm32mp1_clk_get_fixed(_HSE); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 782 | break; |
| 783 | case RCC_ASSCKSELR_PLL: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 784 | clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 785 | break; |
| 786 | default: |
| 787 | break; |
| 788 | } |
| 789 | |
| 790 | /* System clock divider */ |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 791 | reg = mmio_read_32(rcc_base + RCC_AXIDIVR); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 792 | clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; |
| 793 | |
| 794 | switch (p) { |
| 795 | case _PCLK4: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 796 | reg = mmio_read_32(rcc_base + RCC_APB4DIVR); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 797 | clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; |
| 798 | break; |
| 799 | case _PCLK5: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 800 | reg = mmio_read_32(rcc_base + RCC_APB5DIVR); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 801 | clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; |
| 802 | break; |
| 803 | default: |
| 804 | break; |
| 805 | } |
| 806 | break; |
Yann Gautier | ed34232 | 2019-02-15 17:33:27 +0100 | [diff] [blame] | 807 | /* MCU sub system */ |
| 808 | case _CK_MCU: |
| 809 | case _PCLK1: |
| 810 | case _PCLK2: |
| 811 | case _PCLK3: |
| 812 | reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); |
| 813 | switch (reg & RCC_SELR_SRC_MASK) { |
| 814 | case RCC_MSSCKSELR_HSI: |
| 815 | clock = stm32mp1_clk_get_fixed(_HSI); |
| 816 | break; |
| 817 | case RCC_MSSCKSELR_HSE: |
| 818 | clock = stm32mp1_clk_get_fixed(_HSE); |
| 819 | break; |
| 820 | case RCC_MSSCKSELR_CSI: |
| 821 | clock = stm32mp1_clk_get_fixed(_CSI); |
| 822 | break; |
| 823 | case RCC_MSSCKSELR_PLL: |
| 824 | clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); |
| 825 | break; |
| 826 | default: |
| 827 | break; |
| 828 | } |
| 829 | |
| 830 | /* MCU clock divider */ |
| 831 | reg = mmio_read_32(rcc_base + RCC_MCUDIVR); |
| 832 | clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; |
| 833 | |
| 834 | switch (p) { |
| 835 | case _PCLK1: |
| 836 | reg = mmio_read_32(rcc_base + RCC_APB1DIVR); |
| 837 | clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; |
| 838 | break; |
| 839 | case _PCLK2: |
| 840 | reg = mmio_read_32(rcc_base + RCC_APB2DIVR); |
| 841 | clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; |
| 842 | break; |
| 843 | case _PCLK3: |
| 844 | reg = mmio_read_32(rcc_base + RCC_APB3DIVR); |
| 845 | clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; |
| 846 | break; |
| 847 | case _CK_MCU: |
| 848 | default: |
| 849 | break; |
| 850 | } |
| 851 | break; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 852 | case _CK_PER: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 853 | reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 854 | switch (reg & RCC_SELR_SRC_MASK) { |
| 855 | case RCC_CPERCKSELR_HSI: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 856 | clock = stm32mp1_clk_get_fixed(_HSI); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 857 | break; |
| 858 | case RCC_CPERCKSELR_HSE: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 859 | clock = stm32mp1_clk_get_fixed(_HSE); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 860 | break; |
| 861 | case RCC_CPERCKSELR_CSI: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 862 | clock = stm32mp1_clk_get_fixed(_CSI); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 863 | break; |
| 864 | default: |
| 865 | break; |
| 866 | } |
| 867 | break; |
| 868 | case _HSI: |
| 869 | case _HSI_KER: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 870 | clock = stm32mp1_clk_get_fixed(_HSI); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 871 | break; |
| 872 | case _CSI: |
| 873 | case _CSI_KER: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 874 | clock = stm32mp1_clk_get_fixed(_CSI); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 875 | break; |
| 876 | case _HSE: |
| 877 | case _HSE_KER: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 878 | clock = stm32mp1_clk_get_fixed(_HSE); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 879 | break; |
| 880 | case _HSE_KER_DIV2: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 881 | clock = stm32mp1_clk_get_fixed(_HSE) >> 1; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 882 | break; |
| 883 | case _LSI: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 884 | clock = stm32mp1_clk_get_fixed(_LSI); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 885 | break; |
| 886 | case _LSE: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 887 | clock = stm32mp1_clk_get_fixed(_LSE); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 888 | break; |
| 889 | /* PLL */ |
| 890 | case _PLL1_P: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 891 | clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 892 | break; |
| 893 | case _PLL1_Q: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 894 | clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 895 | break; |
| 896 | case _PLL1_R: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 897 | clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 898 | break; |
| 899 | case _PLL2_P: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 900 | clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 901 | break; |
| 902 | case _PLL2_Q: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 903 | clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 904 | break; |
| 905 | case _PLL2_R: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 906 | clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 907 | break; |
| 908 | case _PLL3_P: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 909 | clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 910 | break; |
| 911 | case _PLL3_Q: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 912 | clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 913 | break; |
| 914 | case _PLL3_R: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 915 | clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 916 | break; |
| 917 | case _PLL4_P: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 918 | clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 919 | break; |
| 920 | case _PLL4_Q: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 921 | clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 922 | break; |
| 923 | case _PLL4_R: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 924 | clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 925 | break; |
| 926 | /* Other */ |
| 927 | case _USB_PHY_48: |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 928 | clock = USB_PHY_48_MHZ; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 929 | break; |
| 930 | default: |
| 931 | break; |
| 932 | } |
| 933 | |
| 934 | return clock; |
| 935 | } |
| 936 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 937 | static void __clk_enable(struct stm32mp1_clk_gate const *gate) |
| 938 | { |
| 939 | uintptr_t rcc_base = stm32mp_rcc_base(); |
| 940 | |
| 941 | if (gate->set_clr != 0U) { |
| 942 | mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); |
| 943 | } else { |
| 944 | mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); |
| 945 | } |
| 946 | |
| 947 | VERBOSE("Clock %d has been enabled", gate->index); |
| 948 | } |
| 949 | |
| 950 | static void __clk_disable(struct stm32mp1_clk_gate const *gate) |
| 951 | { |
| 952 | uintptr_t rcc_base = stm32mp_rcc_base(); |
| 953 | |
| 954 | if (gate->set_clr != 0U) { |
| 955 | mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, |
| 956 | BIT(gate->bit)); |
| 957 | } else { |
| 958 | mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); |
| 959 | } |
| 960 | |
| 961 | VERBOSE("Clock %d has been disabled", gate->index); |
| 962 | } |
| 963 | |
| 964 | static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) |
| 965 | { |
| 966 | uintptr_t rcc_base = stm32mp_rcc_base(); |
| 967 | |
| 968 | return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); |
| 969 | } |
| 970 | |
| 971 | unsigned int stm32mp1_clk_get_refcount(unsigned long id) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 972 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 973 | int i = stm32mp1_clk_get_gated_id(id); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 974 | |
| 975 | if (i < 0) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 976 | panic(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 977 | } |
| 978 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 979 | return gate_refcounts[i]; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 980 | } |
| 981 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 982 | void __stm32mp1_clk_enable(unsigned long id, bool secure) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 983 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 984 | const struct stm32mp1_clk_gate *gate; |
| 985 | int i = stm32mp1_clk_get_gated_id(id); |
| 986 | unsigned int *refcnt; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 987 | |
| 988 | if (i < 0) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 989 | ERROR("Clock %d can't be enabled\n", (uint32_t)id); |
| 990 | panic(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 991 | } |
| 992 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 993 | gate = gate_ref(i); |
| 994 | refcnt = &gate_refcounts[i]; |
| 995 | |
| 996 | stm32mp1_clk_lock(&refcount_lock); |
| 997 | |
| 998 | if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) { |
| 999 | __clk_enable(gate); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1000 | } |
| 1001 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1002 | stm32mp1_clk_unlock(&refcount_lock); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1003 | } |
| 1004 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1005 | void __stm32mp1_clk_disable(unsigned long id, bool secure) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1006 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1007 | const struct stm32mp1_clk_gate *gate; |
| 1008 | int i = stm32mp1_clk_get_gated_id(id); |
| 1009 | unsigned int *refcnt; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1010 | |
| 1011 | if (i < 0) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1012 | ERROR("Clock %d can't be disabled\n", (uint32_t)id); |
| 1013 | panic(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1014 | } |
| 1015 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1016 | gate = gate_ref(i); |
| 1017 | refcnt = &gate_refcounts[i]; |
| 1018 | |
| 1019 | stm32mp1_clk_lock(&refcount_lock); |
| 1020 | |
| 1021 | if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) { |
| 1022 | __clk_disable(gate); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1023 | } |
| 1024 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1025 | stm32mp1_clk_unlock(&refcount_lock); |
| 1026 | } |
| 1027 | |
| 1028 | void stm32mp_clk_enable(unsigned long id) |
| 1029 | { |
| 1030 | __stm32mp1_clk_enable(id, true); |
| 1031 | } |
| 1032 | |
| 1033 | void stm32mp_clk_disable(unsigned long id) |
| 1034 | { |
| 1035 | __stm32mp1_clk_disable(id, true); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1036 | } |
| 1037 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1038 | bool stm32mp_clk_is_enabled(unsigned long id) |
| 1039 | { |
| 1040 | int i = stm32mp1_clk_get_gated_id(id); |
| 1041 | |
| 1042 | if (i < 0) { |
| 1043 | panic(); |
| 1044 | } |
| 1045 | |
| 1046 | return __clk_is_enabled(gate_ref(i)); |
| 1047 | } |
| 1048 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 1049 | unsigned long stm32mp_clk_get_rate(unsigned long id) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1050 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1051 | int p = stm32mp1_clk_get_parent(id); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1052 | |
| 1053 | if (p < 0) { |
| 1054 | return 0; |
| 1055 | } |
| 1056 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1057 | return get_clock_rate(p); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1058 | } |
| 1059 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1060 | static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1061 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1062 | uintptr_t address = stm32mp_rcc_base() + offset; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1063 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1064 | if (enable) { |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1065 | mmio_setbits_32(address, mask_on); |
| 1066 | } else { |
| 1067 | mmio_clrbits_32(address, mask_on); |
| 1068 | } |
| 1069 | } |
| 1070 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1071 | static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1072 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1073 | uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; |
| 1074 | uintptr_t address = stm32mp_rcc_base() + offset; |
| 1075 | |
| 1076 | mmio_write_32(address, mask_on); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1077 | } |
| 1078 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1079 | static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1080 | { |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1081 | uint64_t timeout; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1082 | uint32_t mask_test; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1083 | uintptr_t address = stm32mp_rcc_base() + offset; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1084 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1085 | if (enable) { |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1086 | mask_test = mask_rdy; |
| 1087 | } else { |
| 1088 | mask_test = 0; |
| 1089 | } |
| 1090 | |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1091 | timeout = timeout_init_us(OSCRDY_TIMEOUT); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1092 | while ((mmio_read_32(address) & mask_rdy) != mask_test) { |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1093 | if (timeout_elapsed(timeout)) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1094 | ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1095 | mask_rdy, address, enable, mmio_read_32(address)); |
| 1096 | return -ETIMEDOUT; |
| 1097 | } |
| 1098 | } |
| 1099 | |
| 1100 | return 0; |
| 1101 | } |
| 1102 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1103 | static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1104 | { |
| 1105 | uint32_t value; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1106 | uintptr_t rcc_base = stm32mp_rcc_base(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1107 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1108 | if (digbyp) { |
| 1109 | mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1110 | } |
| 1111 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1112 | if (bypass || digbyp) { |
| 1113 | mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); |
| 1114 | } |
| 1115 | |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1116 | /* |
| 1117 | * Warning: not recommended to switch directly from "high drive" |
| 1118 | * to "medium low drive", and vice-versa. |
| 1119 | */ |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1120 | value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1121 | RCC_BDCR_LSEDRV_SHIFT; |
| 1122 | |
| 1123 | while (value != lsedrv) { |
| 1124 | if (value > lsedrv) { |
| 1125 | value--; |
| 1126 | } else { |
| 1127 | value++; |
| 1128 | } |
| 1129 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1130 | mmio_clrsetbits_32(rcc_base + RCC_BDCR, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1131 | RCC_BDCR_LSEDRV_MASK, |
| 1132 | value << RCC_BDCR_LSEDRV_SHIFT); |
| 1133 | } |
| 1134 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1135 | stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1136 | } |
| 1137 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1138 | static void stm32mp1_lse_wait(void) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1139 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1140 | if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1141 | VERBOSE("%s: failed\n", __func__); |
| 1142 | } |
| 1143 | } |
| 1144 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1145 | static void stm32mp1_lsi_set(bool enable) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1146 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1147 | stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); |
| 1148 | |
| 1149 | if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1150 | VERBOSE("%s: failed\n", __func__); |
| 1151 | } |
| 1152 | } |
| 1153 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1154 | static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1155 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1156 | uintptr_t rcc_base = stm32mp_rcc_base(); |
| 1157 | |
| 1158 | if (digbyp) { |
| 1159 | mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1160 | } |
| 1161 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1162 | if (bypass || digbyp) { |
| 1163 | mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); |
| 1164 | } |
| 1165 | |
| 1166 | stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); |
| 1167 | if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1168 | VERBOSE("%s: failed\n", __func__); |
| 1169 | } |
| 1170 | |
| 1171 | if (css) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1172 | mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1173 | } |
| 1174 | } |
| 1175 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1176 | static void stm32mp1_csi_set(bool enable) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1177 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1178 | stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); |
| 1179 | if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1180 | VERBOSE("%s: failed\n", __func__); |
| 1181 | } |
| 1182 | } |
| 1183 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1184 | static void stm32mp1_hsi_set(bool enable) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1185 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1186 | stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); |
| 1187 | if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1188 | VERBOSE("%s: failed\n", __func__); |
| 1189 | } |
| 1190 | } |
| 1191 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1192 | static int stm32mp1_set_hsidiv(uint8_t hsidiv) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1193 | { |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1194 | uint64_t timeout; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1195 | uintptr_t rcc_base = stm32mp_rcc_base(); |
| 1196 | uintptr_t address = rcc_base + RCC_OCRDYR; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1197 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1198 | mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1199 | RCC_HSICFGR_HSIDIV_MASK, |
| 1200 | RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); |
| 1201 | |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1202 | timeout = timeout_init_us(HSIDIV_TIMEOUT); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1203 | while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1204 | if (timeout_elapsed(timeout)) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1205 | ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1206 | address, mmio_read_32(address)); |
| 1207 | return -ETIMEDOUT; |
| 1208 | } |
| 1209 | } |
| 1210 | |
| 1211 | return 0; |
| 1212 | } |
| 1213 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1214 | static int stm32mp1_hsidiv(unsigned long hsifreq) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1215 | { |
| 1216 | uint8_t hsidiv; |
| 1217 | uint32_t hsidivfreq = MAX_HSI_HZ; |
| 1218 | |
| 1219 | for (hsidiv = 0; hsidiv < 4U; hsidiv++) { |
| 1220 | if (hsidivfreq == hsifreq) { |
| 1221 | break; |
| 1222 | } |
| 1223 | |
| 1224 | hsidivfreq /= 2U; |
| 1225 | } |
| 1226 | |
| 1227 | if (hsidiv == 4U) { |
| 1228 | ERROR("Invalid clk-hsi frequency\n"); |
| 1229 | return -1; |
| 1230 | } |
| 1231 | |
| 1232 | if (hsidiv != 0U) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1233 | return stm32mp1_set_hsidiv(hsidiv); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1234 | } |
| 1235 | |
| 1236 | return 0; |
| 1237 | } |
| 1238 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1239 | static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, |
| 1240 | unsigned int clksrc, |
| 1241 | uint32_t *pllcfg, int plloff) |
| 1242 | { |
| 1243 | const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); |
| 1244 | uintptr_t rcc_base = stm32mp_rcc_base(); |
| 1245 | uintptr_t pllxcr = rcc_base + pll->pllxcr; |
| 1246 | enum stm32mp1_plltype type = pll->plltype; |
| 1247 | uintptr_t clksrc_address = rcc_base + (clksrc >> 4); |
| 1248 | unsigned long refclk; |
| 1249 | uint32_t ifrge = 0U; |
| 1250 | uint32_t src, value, fracv; |
| 1251 | |
| 1252 | /* Check PLL output */ |
| 1253 | if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { |
| 1254 | return false; |
| 1255 | } |
| 1256 | |
| 1257 | /* Check current clksrc */ |
| 1258 | src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; |
| 1259 | if (src != (clksrc & RCC_SELR_SRC_MASK)) { |
| 1260 | return false; |
| 1261 | } |
| 1262 | |
| 1263 | /* Check Div */ |
| 1264 | src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; |
| 1265 | |
| 1266 | refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / |
| 1267 | (pllcfg[PLLCFG_M] + 1U); |
| 1268 | |
| 1269 | if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || |
| 1270 | (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { |
| 1271 | return false; |
| 1272 | } |
| 1273 | |
| 1274 | if ((type == PLL_800) && (refclk >= 8000000U)) { |
| 1275 | ifrge = 1U; |
| 1276 | } |
| 1277 | |
| 1278 | value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & |
| 1279 | RCC_PLLNCFGR1_DIVN_MASK; |
| 1280 | value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & |
| 1281 | RCC_PLLNCFGR1_DIVM_MASK; |
| 1282 | value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & |
| 1283 | RCC_PLLNCFGR1_IFRGE_MASK; |
| 1284 | if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { |
| 1285 | return false; |
| 1286 | } |
| 1287 | |
| 1288 | /* Fractional configuration */ |
| 1289 | fracv = fdt_read_uint32_default(plloff, "frac", 0); |
| 1290 | |
| 1291 | value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; |
| 1292 | value |= RCC_PLLNFRACR_FRACLE; |
| 1293 | if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { |
| 1294 | return false; |
| 1295 | } |
| 1296 | |
| 1297 | /* Output config */ |
| 1298 | value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & |
| 1299 | RCC_PLLNCFGR2_DIVP_MASK; |
| 1300 | value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & |
| 1301 | RCC_PLLNCFGR2_DIVQ_MASK; |
| 1302 | value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & |
| 1303 | RCC_PLLNCFGR2_DIVR_MASK; |
| 1304 | if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { |
| 1305 | return false; |
| 1306 | } |
| 1307 | |
| 1308 | return true; |
| 1309 | } |
| 1310 | |
| 1311 | static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1312 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1313 | const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); |
| 1314 | uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1315 | |
Yann Gautier | d0dcbaa | 2019-06-04 15:55:37 +0200 | [diff] [blame] | 1316 | /* Preserve RCC_PLLNCR_SSCG_CTRL value */ |
| 1317 | mmio_clrsetbits_32(pllxcr, |
| 1318 | RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | |
| 1319 | RCC_PLLNCR_DIVREN, |
| 1320 | RCC_PLLNCR_PLLON); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1321 | } |
| 1322 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1323 | static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1324 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1325 | const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); |
| 1326 | uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1327 | uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1328 | |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1329 | /* Wait PLL lock */ |
| 1330 | while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1331 | if (timeout_elapsed(timeout)) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1332 | ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1333 | pll_id, pllxcr, mmio_read_32(pllxcr)); |
| 1334 | return -ETIMEDOUT; |
| 1335 | } |
| 1336 | } |
| 1337 | |
| 1338 | /* Start the requested output */ |
| 1339 | mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); |
| 1340 | |
| 1341 | return 0; |
| 1342 | } |
| 1343 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1344 | static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1345 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1346 | const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); |
| 1347 | uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1348 | uint64_t timeout; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1349 | |
| 1350 | /* Stop all output */ |
| 1351 | mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | |
| 1352 | RCC_PLLNCR_DIVREN); |
| 1353 | |
| 1354 | /* Stop PLL */ |
| 1355 | mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); |
| 1356 | |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1357 | timeout = timeout_init_us(PLLRDY_TIMEOUT); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1358 | /* Wait PLL stopped */ |
| 1359 | while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1360 | if (timeout_elapsed(timeout)) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1361 | ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1362 | pll_id, pllxcr, mmio_read_32(pllxcr)); |
| 1363 | return -ETIMEDOUT; |
| 1364 | } |
| 1365 | } |
| 1366 | |
| 1367 | return 0; |
| 1368 | } |
| 1369 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1370 | static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1371 | uint32_t *pllcfg) |
| 1372 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1373 | const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); |
| 1374 | uintptr_t rcc_base = stm32mp_rcc_base(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1375 | uint32_t value; |
| 1376 | |
| 1377 | value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & |
| 1378 | RCC_PLLNCFGR2_DIVP_MASK; |
| 1379 | value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & |
| 1380 | RCC_PLLNCFGR2_DIVQ_MASK; |
| 1381 | value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & |
| 1382 | RCC_PLLNCFGR2_DIVR_MASK; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1383 | mmio_write_32(rcc_base + pll->pllxcfgr2, value); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1384 | } |
| 1385 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1386 | static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1387 | uint32_t *pllcfg, uint32_t fracv) |
| 1388 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1389 | const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); |
| 1390 | uintptr_t rcc_base = stm32mp_rcc_base(); |
| 1391 | enum stm32mp1_plltype type = pll->plltype; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1392 | unsigned long refclk; |
| 1393 | uint32_t ifrge = 0; |
| 1394 | uint32_t src, value; |
| 1395 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1396 | src = mmio_read_32(rcc_base + pll->rckxselr) & |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1397 | RCC_SELR_REFCLK_SRC_MASK; |
| 1398 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1399 | refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1400 | (pllcfg[PLLCFG_M] + 1U); |
| 1401 | |
| 1402 | if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || |
| 1403 | (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { |
| 1404 | return -EINVAL; |
| 1405 | } |
| 1406 | |
| 1407 | if ((type == PLL_800) && (refclk >= 8000000U)) { |
| 1408 | ifrge = 1U; |
| 1409 | } |
| 1410 | |
| 1411 | value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & |
| 1412 | RCC_PLLNCFGR1_DIVN_MASK; |
| 1413 | value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & |
| 1414 | RCC_PLLNCFGR1_DIVM_MASK; |
| 1415 | value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & |
| 1416 | RCC_PLLNCFGR1_IFRGE_MASK; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1417 | mmio_write_32(rcc_base + pll->pllxcfgr1, value); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1418 | |
| 1419 | /* Fractional configuration */ |
| 1420 | value = 0; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1421 | mmio_write_32(rcc_base + pll->pllxfracr, value); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1422 | |
| 1423 | value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1424 | mmio_write_32(rcc_base + pll->pllxfracr, value); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1425 | |
| 1426 | value |= RCC_PLLNFRACR_FRACLE; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1427 | mmio_write_32(rcc_base + pll->pllxfracr, value); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1428 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1429 | stm32mp1_pll_config_output(pll_id, pllcfg); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1430 | |
| 1431 | return 0; |
| 1432 | } |
| 1433 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1434 | static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1435 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1436 | const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1437 | uint32_t pllxcsg = 0; |
| 1438 | |
| 1439 | pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & |
| 1440 | RCC_PLLNCSGR_MOD_PER_MASK; |
| 1441 | |
| 1442 | pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & |
| 1443 | RCC_PLLNCSGR_INC_STEP_MASK; |
| 1444 | |
| 1445 | pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & |
| 1446 | RCC_PLLNCSGR_SSCG_MODE_MASK; |
| 1447 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1448 | mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); |
Yann Gautier | d0dcbaa | 2019-06-04 15:55:37 +0200 | [diff] [blame] | 1449 | |
| 1450 | mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, |
| 1451 | RCC_PLLNCR_SSCG_CTRL); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1452 | } |
| 1453 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1454 | static int stm32mp1_set_clksrc(unsigned int clksrc) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1455 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1456 | uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1457 | uint64_t timeout; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1458 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1459 | mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1460 | clksrc & RCC_SELR_SRC_MASK); |
| 1461 | |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1462 | timeout = timeout_init_us(CLKSRC_TIMEOUT); |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1463 | while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1464 | if (timeout_elapsed(timeout)) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1465 | ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, |
| 1466 | clksrc_address, mmio_read_32(clksrc_address)); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1467 | return -ETIMEDOUT; |
| 1468 | } |
| 1469 | } |
| 1470 | |
| 1471 | return 0; |
| 1472 | } |
| 1473 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1474 | static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1475 | { |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1476 | uint64_t timeout; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1477 | |
| 1478 | mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, |
| 1479 | clkdiv & RCC_DIVR_DIV_MASK); |
| 1480 | |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1481 | timeout = timeout_init_us(CLKDIV_TIMEOUT); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1482 | while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { |
Yann Gautier | 2299d57 | 2019-02-14 11:14:39 +0100 | [diff] [blame] | 1483 | if (timeout_elapsed(timeout)) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1484 | ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1485 | clkdiv, address, mmio_read_32(address)); |
| 1486 | return -ETIMEDOUT; |
| 1487 | } |
| 1488 | } |
| 1489 | |
| 1490 | return 0; |
| 1491 | } |
| 1492 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1493 | static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1494 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1495 | uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1496 | |
| 1497 | /* |
| 1498 | * Binding clksrc : |
| 1499 | * bit15-4 offset |
| 1500 | * bit3: disable |
| 1501 | * bit2-0: MCOSEL[2:0] |
| 1502 | */ |
| 1503 | if ((clksrc & 0x8U) != 0U) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1504 | mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1505 | } else { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1506 | mmio_clrsetbits_32(clksrc_address, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1507 | RCC_MCOCFG_MCOSRC_MASK, |
| 1508 | clksrc & RCC_MCOCFG_MCOSRC_MASK); |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1509 | mmio_clrsetbits_32(clksrc_address, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1510 | RCC_MCOCFG_MCODIV_MASK, |
| 1511 | clkdiv << RCC_MCOCFG_MCODIV_SHIFT); |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1512 | mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1513 | } |
| 1514 | } |
| 1515 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1516 | static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1517 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1518 | uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1519 | |
| 1520 | if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || |
| 1521 | (clksrc != (uint32_t)CLK_RTC_DISABLED)) { |
| 1522 | mmio_clrsetbits_32(address, |
| 1523 | RCC_BDCR_RTCSRC_MASK, |
| 1524 | clksrc << RCC_BDCR_RTCSRC_SHIFT); |
| 1525 | |
| 1526 | mmio_setbits_32(address, RCC_BDCR_RTCCKEN); |
| 1527 | } |
| 1528 | |
| 1529 | if (lse_css) { |
| 1530 | mmio_setbits_32(address, RCC_BDCR_LSECSSON); |
| 1531 | } |
| 1532 | } |
| 1533 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1534 | static void stm32mp1_stgen_config(void) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1535 | { |
| 1536 | uintptr_t stgen; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1537 | uint32_t cntfid0; |
| 1538 | unsigned long rate; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1539 | unsigned long long counter; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1540 | |
| 1541 | stgen = fdt_get_stgen_base(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1542 | cntfid0 = mmio_read_32(stgen + CNTFID_OFF); |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1543 | rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1544 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1545 | if (cntfid0 == rate) { |
| 1546 | return; |
| 1547 | } |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1548 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1549 | mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); |
| 1550 | counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF); |
| 1551 | counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32; |
| 1552 | counter = (counter * rate / cntfid0); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1553 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1554 | mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter); |
| 1555 | mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32)); |
| 1556 | mmio_write_32(stgen + CNTFID_OFF, rate); |
| 1557 | mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1558 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1559 | write_cntfrq((u_register_t)rate); |
| 1560 | |
| 1561 | /* Need to update timer with new frequency */ |
| 1562 | generic_delay_timer_init(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1563 | } |
| 1564 | |
| 1565 | void stm32mp1_stgen_increment(unsigned long long offset_in_ms) |
| 1566 | { |
| 1567 | uintptr_t stgen; |
| 1568 | unsigned long long cnt; |
| 1569 | |
| 1570 | stgen = fdt_get_stgen_base(); |
| 1571 | |
| 1572 | cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) | |
| 1573 | mmio_read_32(stgen + CNTCVL_OFF); |
| 1574 | |
| 1575 | cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U; |
| 1576 | |
| 1577 | mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); |
| 1578 | mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt); |
| 1579 | mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32)); |
| 1580 | mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); |
| 1581 | } |
| 1582 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1583 | static void stm32mp1_pkcs_config(uint32_t pkcs) |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1584 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1585 | uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1586 | uint32_t value = pkcs & 0xFU; |
| 1587 | uint32_t mask = 0xFU; |
| 1588 | |
| 1589 | if ((pkcs & BIT(31)) != 0U) { |
| 1590 | mask <<= 4; |
| 1591 | value <<= 4; |
| 1592 | } |
| 1593 | |
| 1594 | mmio_clrsetbits_32(address, mask, value); |
| 1595 | } |
| 1596 | |
| 1597 | int stm32mp1_clk_init(void) |
| 1598 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1599 | uintptr_t rcc_base = stm32mp_rcc_base(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1600 | unsigned int clksrc[CLKSRC_NB]; |
| 1601 | unsigned int clkdiv[CLKDIV_NB]; |
| 1602 | unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; |
| 1603 | int plloff[_PLL_NB]; |
| 1604 | int ret, len; |
| 1605 | enum stm32mp1_pll_id i; |
| 1606 | bool lse_css = false; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1607 | bool pll3_preserve = false; |
| 1608 | bool pll4_preserve = false; |
| 1609 | bool pll4_bootrom = false; |
Yann Gautier | f9af3bc | 2018-11-09 15:57:18 +0100 | [diff] [blame] | 1610 | const fdt32_t *pkcs_cell; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1611 | |
| 1612 | /* Check status field to disable security */ |
| 1613 | if (!fdt_get_rcc_secure_status()) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1614 | mmio_write_32(rcc_base + RCC_TZCR, 0); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1615 | } |
| 1616 | |
| 1617 | ret = fdt_rcc_read_uint32_array("st,clksrc", clksrc, |
| 1618 | (uint32_t)CLKSRC_NB); |
| 1619 | if (ret < 0) { |
| 1620 | return -FDT_ERR_NOTFOUND; |
| 1621 | } |
| 1622 | |
| 1623 | ret = fdt_rcc_read_uint32_array("st,clkdiv", clkdiv, |
| 1624 | (uint32_t)CLKDIV_NB); |
| 1625 | if (ret < 0) { |
| 1626 | return -FDT_ERR_NOTFOUND; |
| 1627 | } |
| 1628 | |
| 1629 | for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { |
| 1630 | char name[12]; |
| 1631 | |
Antonio Nino Diaz | 00086e3 | 2018-08-16 16:46:06 +0100 | [diff] [blame] | 1632 | snprintf(name, sizeof(name), "st,pll@%d", i); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1633 | plloff[i] = fdt_rcc_subnode_offset(name); |
| 1634 | |
| 1635 | if (!fdt_check_node(plloff[i])) { |
| 1636 | continue; |
| 1637 | } |
| 1638 | |
| 1639 | ret = fdt_read_uint32_array(plloff[i], "cfg", |
| 1640 | pllcfg[i], (int)PLLCFG_NB); |
| 1641 | if (ret < 0) { |
| 1642 | return -FDT_ERR_NOTFOUND; |
| 1643 | } |
| 1644 | } |
| 1645 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1646 | stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); |
| 1647 | stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1648 | |
| 1649 | /* |
| 1650 | * Switch ON oscillator found in device-tree. |
| 1651 | * Note: HSI already ON after BootROM stage. |
| 1652 | */ |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1653 | if (stm32mp1_osc[_LSI] != 0U) { |
| 1654 | stm32mp1_lsi_set(true); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1655 | } |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1656 | if (stm32mp1_osc[_LSE] != 0U) { |
| 1657 | bool bypass, digbyp; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1658 | uint32_t lsedrv; |
| 1659 | |
| 1660 | bypass = fdt_osc_read_bool(_LSE, "st,bypass"); |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1661 | digbyp = fdt_osc_read_bool(_LSE, "st,digbypass"); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1662 | lse_css = fdt_osc_read_bool(_LSE, "st,css"); |
| 1663 | lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive", |
| 1664 | LSEDRV_MEDIUM_HIGH); |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1665 | stm32mp1_lse_enable(bypass, digbyp, lsedrv); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1666 | } |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1667 | if (stm32mp1_osc[_HSE] != 0U) { |
| 1668 | bool bypass, digbyp, css; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1669 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1670 | bypass = fdt_osc_read_bool(_HSE, "st,bypass"); |
| 1671 | digbyp = fdt_osc_read_bool(_HSE, "st,digbypass"); |
| 1672 | css = fdt_osc_read_bool(_HSE, "st,css"); |
| 1673 | stm32mp1_hse_enable(bypass, digbyp, css); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1674 | } |
| 1675 | /* |
| 1676 | * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) |
| 1677 | * => switch on CSI even if node is not present in device tree |
| 1678 | */ |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1679 | stm32mp1_csi_set(true); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1680 | |
| 1681 | /* Come back to HSI */ |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1682 | ret = stm32mp1_set_clksrc(CLK_MPU_HSI); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1683 | if (ret != 0) { |
| 1684 | return ret; |
| 1685 | } |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1686 | ret = stm32mp1_set_clksrc(CLK_AXI_HSI); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1687 | if (ret != 0) { |
| 1688 | return ret; |
| 1689 | } |
Yann Gautier | ed34232 | 2019-02-15 17:33:27 +0100 | [diff] [blame] | 1690 | ret = stm32mp1_set_clksrc(CLK_MCU_HSI); |
| 1691 | if (ret != 0) { |
| 1692 | return ret; |
| 1693 | } |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1694 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1695 | if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & |
| 1696 | RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { |
| 1697 | pll3_preserve = stm32mp1_check_pll_conf(_PLL3, |
| 1698 | clksrc[CLKSRC_PLL3], |
| 1699 | pllcfg[_PLL3], |
| 1700 | plloff[_PLL3]); |
| 1701 | pll4_preserve = stm32mp1_check_pll_conf(_PLL4, |
| 1702 | clksrc[CLKSRC_PLL4], |
| 1703 | pllcfg[_PLL4], |
| 1704 | plloff[_PLL4]); |
| 1705 | } |
| 1706 | |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1707 | for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1708 | if (((i == _PLL3) && pll3_preserve) || |
| 1709 | ((i == _PLL4) && pll4_preserve)) { |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1710 | continue; |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1711 | } |
| 1712 | |
| 1713 | ret = stm32mp1_pll_stop(i); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1714 | if (ret != 0) { |
| 1715 | return ret; |
| 1716 | } |
| 1717 | } |
| 1718 | |
| 1719 | /* Configure HSIDIV */ |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1720 | if (stm32mp1_osc[_HSI] != 0U) { |
| 1721 | ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1722 | if (ret != 0) { |
| 1723 | return ret; |
| 1724 | } |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1725 | stm32mp1_stgen_config(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1726 | } |
| 1727 | |
| 1728 | /* Select DIV */ |
| 1729 | /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1730 | mmio_write_32(rcc_base + RCC_MPCKDIVR, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1731 | clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1732 | ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1733 | if (ret != 0) { |
| 1734 | return ret; |
| 1735 | } |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1736 | ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1737 | if (ret != 0) { |
| 1738 | return ret; |
| 1739 | } |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1740 | ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1741 | if (ret != 0) { |
| 1742 | return ret; |
| 1743 | } |
Yann Gautier | ed34232 | 2019-02-15 17:33:27 +0100 | [diff] [blame] | 1744 | ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); |
| 1745 | if (ret != 0) { |
| 1746 | return ret; |
| 1747 | } |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1748 | ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1749 | if (ret != 0) { |
| 1750 | return ret; |
| 1751 | } |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1752 | ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1753 | if (ret != 0) { |
| 1754 | return ret; |
| 1755 | } |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1756 | ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1757 | if (ret != 0) { |
| 1758 | return ret; |
| 1759 | } |
| 1760 | |
| 1761 | /* No ready bit for RTC */ |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1762 | mmio_write_32(rcc_base + RCC_RTCDIVR, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1763 | clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); |
| 1764 | |
| 1765 | /* Configure PLLs source */ |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1766 | ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1767 | if (ret != 0) { |
| 1768 | return ret; |
| 1769 | } |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1770 | |
| 1771 | if (!pll3_preserve) { |
| 1772 | ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); |
| 1773 | if (ret != 0) { |
| 1774 | return ret; |
| 1775 | } |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1776 | } |
| 1777 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1778 | if (!pll4_preserve) { |
| 1779 | ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); |
| 1780 | if (ret != 0) { |
| 1781 | return ret; |
| 1782 | } |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1783 | } |
| 1784 | |
| 1785 | /* Configure and start PLLs */ |
| 1786 | for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { |
| 1787 | uint32_t fracv; |
| 1788 | uint32_t csg[PLLCSG_NB]; |
| 1789 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1790 | if (((i == _PLL3) && pll3_preserve) || |
| 1791 | ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { |
| 1792 | continue; |
| 1793 | } |
| 1794 | |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1795 | if (!fdt_check_node(plloff[i])) { |
| 1796 | continue; |
| 1797 | } |
| 1798 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1799 | if ((i == _PLL4) && pll4_bootrom) { |
| 1800 | /* Set output divider if not done by the Bootrom */ |
| 1801 | stm32mp1_pll_config_output(i, pllcfg[i]); |
| 1802 | continue; |
| 1803 | } |
| 1804 | |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1805 | fracv = fdt_read_uint32_default(plloff[i], "frac", 0); |
| 1806 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1807 | ret = stm32mp1_pll_config(i, pllcfg[i], fracv); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1808 | if (ret != 0) { |
| 1809 | return ret; |
| 1810 | } |
| 1811 | ret = fdt_read_uint32_array(plloff[i], "csg", csg, |
| 1812 | (uint32_t)PLLCSG_NB); |
| 1813 | if (ret == 0) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1814 | stm32mp1_pll_csg(i, csg); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1815 | } else if (ret != -FDT_ERR_NOTFOUND) { |
| 1816 | return ret; |
| 1817 | } |
| 1818 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1819 | stm32mp1_pll_start(i); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1820 | } |
| 1821 | /* Wait and start PLLs ouptut when ready */ |
| 1822 | for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { |
| 1823 | if (!fdt_check_node(plloff[i])) { |
| 1824 | continue; |
| 1825 | } |
| 1826 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1827 | ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1828 | if (ret != 0) { |
| 1829 | return ret; |
| 1830 | } |
| 1831 | } |
| 1832 | /* Wait LSE ready before to use it */ |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1833 | if (stm32mp1_osc[_LSE] != 0U) { |
| 1834 | stm32mp1_lse_wait(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1835 | } |
| 1836 | |
| 1837 | /* Configure with expected clock source */ |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1838 | ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1839 | if (ret != 0) { |
| 1840 | return ret; |
| 1841 | } |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1842 | ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1843 | if (ret != 0) { |
| 1844 | return ret; |
| 1845 | } |
Yann Gautier | ed34232 | 2019-02-15 17:33:27 +0100 | [diff] [blame] | 1846 | ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); |
| 1847 | if (ret != 0) { |
| 1848 | return ret; |
| 1849 | } |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1850 | stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1851 | |
| 1852 | /* Configure PKCK */ |
| 1853 | pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); |
| 1854 | if (pkcs_cell != NULL) { |
| 1855 | bool ckper_disabled = false; |
| 1856 | uint32_t j; |
| 1857 | |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1858 | for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { |
Yann Gautier | f9af3bc | 2018-11-09 15:57:18 +0100 | [diff] [blame] | 1859 | uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1860 | |
| 1861 | if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { |
| 1862 | ckper_disabled = true; |
| 1863 | continue; |
| 1864 | } |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1865 | stm32mp1_pkcs_config(pkcs); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1866 | } |
| 1867 | |
| 1868 | /* |
| 1869 | * CKPER is source for some peripheral clocks |
| 1870 | * (FMC-NAND / QPSI-NOR) and switching source is allowed |
| 1871 | * only if previous clock is still ON |
| 1872 | * => deactivated CKPER only after switching clock |
| 1873 | */ |
| 1874 | if (ckper_disabled) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1875 | stm32mp1_pkcs_config(CLK_CKPER_DISABLED); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1876 | } |
| 1877 | } |
| 1878 | |
| 1879 | /* Switch OFF HSI if not found in device-tree */ |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1880 | if (stm32mp1_osc[_HSI] == 0U) { |
| 1881 | stm32mp1_hsi_set(false); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1882 | } |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1883 | stm32mp1_stgen_config(); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1884 | |
| 1885 | /* Software Self-Refresh mode (SSR) during DDR initilialization */ |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1886 | mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1887 | RCC_DDRITFCR_DDRCKMOD_MASK, |
| 1888 | RCC_DDRITFCR_DDRCKMOD_SSR << |
| 1889 | RCC_DDRITFCR_DDRCKMOD_SHIFT); |
| 1890 | |
| 1891 | return 0; |
| 1892 | } |
| 1893 | |
| 1894 | static void stm32mp1_osc_clk_init(const char *name, |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1895 | enum stm32mp_osc_id index) |
| 1896 | { |
| 1897 | uint32_t frequency; |
| 1898 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1899 | if (fdt_osc_read_freq(name, &frequency) == 0) { |
| 1900 | stm32mp1_osc[index] = frequency; |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1901 | } |
| 1902 | } |
| 1903 | |
| 1904 | static void stm32mp1_osc_init(void) |
| 1905 | { |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1906 | enum stm32mp_osc_id i; |
| 1907 | |
| 1908 | for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 1909 | stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1910 | } |
| 1911 | } |
| 1912 | |
| 1913 | int stm32mp1_clk_probe(void) |
| 1914 | { |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 1915 | stm32mp1_osc_init(); |
| 1916 | |
| 1917 | return 0; |
| 1918 | } |