| Nishanth Menon | f49cf9e | 2017-09-20 01:32:13 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 7 | #ifndef BOARD_DEF_H |
| 8 | #define BOARD_DEF_H |
| 9 | |
| 10 | #include <utils_def.h> |
| Nishanth Menon | f49cf9e | 2017-09-20 01:32:13 -0500 | [diff] [blame] | 11 | |
| 12 | /* The ports must be in order and contiguous */ |
| 13 | #define K3_CLUSTER0_CORE_COUNT 2 |
| 14 | #define K3_CLUSTER0_MSMC_PORT 0 |
| 15 | |
| 16 | #define K3_CLUSTER1_CORE_COUNT 2 |
| 17 | #define K3_CLUSTER1_MSMC_PORT 1 |
| 18 | |
| 19 | #define K3_CLUSTER2_CORE_COUNT 2 |
| 20 | #define K3_CLUSTER2_MSMC_PORT 2 |
| 21 | |
| 22 | #define K3_CLUSTER3_CORE_COUNT 2 |
| 23 | #define K3_CLUSTER3_MSMC_PORT 3 |
| 24 | |
| 25 | /* |
| 26 | * This RAM will be used for the bootloader including code, bss, and stacks. |
| 27 | * It may need to be increased if BL31 grows in size. |
| 28 | */ |
| 29 | #define SEC_SRAM_BASE 0x70000000 /* Base of MSMC SRAM */ |
| 30 | #define SEC_SRAM_SIZE 0x00020000 /* 128k */ |
| 31 | |
| Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 32 | #define PLAT_MAX_OFF_STATE U(2) |
| 33 | #define PLAT_MAX_RET_STATE U(1) |
| Nishanth Menon | f49cf9e | 2017-09-20 01:32:13 -0500 | [diff] [blame] | 34 | |
| Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 35 | #endif /* BOARD_DEF_H */ |