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git01.mediatek.com / filogic / atf / 3e91a7602f3d9ca74aadaf208699351da576ede1 / . / plat / imx / imx8m / imx8mn / include / imx_sec_def.h
blob: 0ef14a90bc1e2182d11ae07c6792e83753fd0251 [file] [log] [blame]
Jacky Bai3e91a762022-03-15 10:29:09 +0800[diff] [blame^]1/*
2 * Copyright 2020-2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef IMX_SEC_DEF_H
8#define IMX_SEC_DEF_H
9
10/* RDC MDA index */
11enum rdc_mda_idx {
12 RDC_MDA_A53 = 0,
13 RDC_MDA_M7 = 1,
14 RDC_MDA_SDMA3p = 3,
15 RDC_MDA_LCDIF = 5,
16 RDC_MDA_ISI = 6,
17 RDC_MDA_SDMA3b = 7,
18 RDC_MDA_Coresight = 8,
19 RDC_MDA_DAP = 9,
20 RDC_MDA_CAAM = 10,
21 RDC_MDA_SDMA1p = 11,
22 RDC_MDA_SDMA1b = 12,
23 RDC_MDA_APBHDMA = 13,
24 RDC_MDA_RAWNAND = 14,
25 RDC_MDA_uSDHC1 = 15,
26 RDC_MDA_uSDHC2 = 16,
27 RDC_MDA_uSDHC3 = 17,
28 RDC_MDA_GPU = 18,
29 RDC_MDA_USB1 = 19,
30 RDC_MDA_TESTPORT = 21,
31 RDC_MDA_ENET1_TX = 22,
32 RDC_MDA_ENET1_RX = 23,
33 RDC_MDA_SDMA2 = 24,
34};
35
36/* RDC Peripherals index */
37enum rdc_pdap_idx {
38 RDC_PDAP_GPIO1 = 0,
39 RDC_PDAP_GPIO2 = 1,
40 RDC_PDAP_GPIO3 = 2,
41 RDC_PDAP_GPIO4 = 3,
42 RDC_PDAP_GPIO5 = 4,
43 RDC_PDAP_ANA_TSENSOR = 6,
44 RDC_PDAP_ANA_OSC = 7,
45 RDC_PDAP_WDOG1 = 8,
46 RDC_PDAP_WDOG2 = 9,
47 RDC_PDAP_WDOG3 = 10,
48 RDC_PDAP_SDMA3 = 11,
49 RDC_PDAP_SDMA2 = 12,
50 RDC_PDAP_GPT1 = 13,
51 RDC_PDAP_GPT2 = 14,
52 RDC_PDAP_GPT3 = 15,
53 RDC_PDAP_ROMCP = 17,
54 RDC_PDAP_IOMUXC = 19,
55 RDC_PDAP_IOMUXC_GPR = 20,
56 RDC_PDAP_OCOTP_CTRL = 21,
57 RDC_PDAP_ANA_PLL = 22,
58 RDC_PDAP_SNVS_HP = 23,
59 RDC_PDAP_CCM = 24,
60 RDC_PDAP_SRC = 25,
61 RDC_PDAP_GPC = 26,
62 RDC_PDAP_SEMAPHORE1 = 27,
63 RDC_PDAP_SEMAPHORE2 = 28,
64 RDC_PDAP_RDC = 29,
65 RDC_PDAP_CSU = 30,
66 RDC_PDAP_LCDIF = 32,
67 RDC_PDAP_MIPI_DSI = 33,
68 RDC_PDAP_ISI = 34,
69 RDC_PDAP_MIPI_CSI = 35,
70 RDC_PDAP_USB1 = 36,
71 RDC_PDAP_PWM1 = 38,
72 RDC_PDAP_PWM2 = 39,
73 RDC_PDAP_PWM3 = 40,
74 RDC_PDAP_PWM4 = 41,
75 RDC_PDAP_System_Counter_RD = 42,
76 RDC_PDAP_System_Counter_CMP = 43,
77 RDC_PDAP_System_Counter_CTRL = 44,
78 RDC_PDAP_GPT6 = 46,
79 RDC_PDAP_GPT5 = 47,
80 RDC_PDAP_GPT4 = 48,
81 RDC_PDAP_TZASC = 56,
82 RDC_PDAP_PERFMON1 = 60,
83 RDC_PDAP_PERFMON2 = 61,
84 RDC_PDAP_PLATFORM_CTRL = 62,
85 RDC_PDAP_QoSC = 63,
86 RDC_PDAP_I2C1 = 66,
87 RDC_PDAP_I2C2 = 67,
88 RDC_PDAP_I2C3 = 68,
89 RDC_PDAP_I2C4 = 69,
90 RDC_PDAP_UART4 = 70,
91 RDC_PDAP_MU_A = 74,
92 RDC_PDAP_MU_B = 75,
93 RDC_PDAP_SEMAPHORE_HS = 76,
94 RDC_PDAP_SAI2 = 79,
95 RDC_PDAP_SAI3 = 80,
96 RDC_PDAP_SAI5 = 82,
97 RDC_PDAP_SAI6 = 83,
98 RDC_PDAP_uSDHC1 = 84,
99 RDC_PDAP_uSDHC2 = 85,
100 RDC_PDAP_uSDHC3 = 86,
101 RDC_PDAP_SAI7 = 87,
102 RDC_PDAP_SPBA2 = 90,
103 RDC_PDAP_QSPI = 91,
104 RDC_PDAP_SDMA1 = 93,
105 RDC_PDAP_ENET1 = 94,
106 RDC_PDAP_SPDIF1 = 97,
107 RDC_PDAP_eCSPI1 = 98,
108 RDC_PDAP_eCSPI2 = 99,
109 RDC_PDAP_eCSPI3 = 100,
110 RDC_PDAP_MICFIL = 101,
111 RDC_PDAP_UART1 = 102,
112 RDC_PDAP_UART3 = 104,
113 RDC_PDAP_UART2 = 105,
114 RDC_PDAP_ASRC = 107,
115 RDC_PDAP_SPBA1 = 111,
116 RDC_PDAP_CAAM = 114,
117};
118
119enum csu_csl_idx {
120 CSU_CSL_GPIO1 = 0,
121 CSU_CSL_GPIO2 = 1,
122 CSU_CSL_GPIO3 = 2,
123 CSU_CSL_GPIO4 = 3,
124 CSU_CSL_GPIO5 = 4,
125 CSU_CSL_ANA_TSENSOR = 6,
126 CSU_CSL_ANA_OSC = 7,
127 CSU_CSL_WDOG1 = 8,
128 CSU_CSL_WDOG2 = 9,
129 CSU_CSL_WDOG3 = 10,
130 CSU_CSL_SDMA2 = 12,
131 CSU_CSL_GPT1 = 13,
132 CSU_CSL_GPT2 = 14,
133 CSU_CSL_GPT3 = 15,
134 CSU_CSL_ROMCP = 17,
135 CSU_CSL_LCDIF = 18,
136 CSU_CSL_IOMUXC = 19,
137 CSU_CSL_IOMUXC_GPR = 20,
138 CSU_CSL_OCOTP_CTRL = 21,
139 CSU_CSL_ANA_PLL = 22,
140 CSU_CSL_SNVS_HP = 23,
141 CSU_CSL_CCM = 24,
142 CSU_CSL_SRC = 25,
143 CSU_CSL_GPC = 26,
144 CSU_CSL_SEMAPHORE1 = 27,
145 CSU_CSL_SEMAPHORE2 = 28,
146 CSU_CSL_RDC = 29,
147 CSU_CSL_CSU = 30,
148 CSU_CSL_DC_MST0 = 32,
149 CSU_CSL_DC_MST1 = 33,
150 CSU_CSL_DC_MST2 = 34,
151 CSU_CSL_DC_MST3 = 35,
152 CSU_CSL_PWM1 = 38,
153 CSU_CSL_PWM2 = 39,
154 CSU_CSL_PWM3 = 40,
155 CSU_CSL_PWM4 = 41,
156 CSU_CSL_System_Counter_RD = 42,
157 CSU_CSL_System_Counter_CMP = 43,
158 CSU_CSL_System_Counter_CTRL = 44,
159 CSU_CSL_GPT6 = 46,
160 CSU_CSL_GPT5 = 47,
161 CSU_CSL_GPT4 = 48,
162 CSU_CSL_TZASC = 56,
163 CSU_CSL_MTR = 59,
164 CSU_CSL_PERFMON1 = 60,
165 CSU_CSL_PERFMON2 = 61,
166 CSU_CSL_PLATFORM_CTRL = 62,
167 CSU_CSL_QoSC = 63,
168 CSU_CSL_MIPI_PHY = 64,
169 CSU_CSL_MIPI_DSI = 65,
170 CSU_CSL_I2C1 = 66,
171 CSU_CSL_I2C2 = 67,
172 CSU_CSL_I2C3 = 68,
173 CSU_CSL_I2C4 = 69,
174 CSU_CSL_UART4 = 70,
175 CSU_CSL_MIPI_CSI1 = 71,
176 CSU_CSL_MIPI_CSI_PHY1 = 72,
177 CSU_CSL_CSI1 = 73,
178 CSU_CSL_MU_A = 74,
179 CSU_CSL_MU_B = 75,
180 CSU_CSL_SEMAPHORE_HS = 76,
181 CSU_CSL_SAI1 = 78,
182 CSU_CSL_SAI6 = 80,
183 CSU_CSL_SAI5 = 81,
184 CSU_CSL_SAI4 = 82,
185 CSU_CSL_uSDHC1 = 84,
186 CSU_CSL_uSDHC2 = 85,
187 CSU_CSL_MIPI_CSI2 = 86,
188 CSU_CSL_MIPI_CSI_PHY2 = 87,
189 CSU_CSL_CSI2 = 88,
190 CSU_CSL_SPBA2 = 90,
191 CSU_CSL_QSPI = 91,
192 CSU_CSL_SDMA1 = 93,
193 CSU_CSL_ENET1 = 94,
194 CSU_CSL_SPDIF1 = 97,
195 CSU_CSL_eCSPI1 = 98,
196 CSU_CSL_eCSPI2 = 99,
197 CSU_CSL_eCSPI3 = 100,
198 CSU_CSL_UART1 = 102,
199 CSU_CSL_UART3 = 104,
200 CSU_CSL_UART2 = 105,
201 CSU_CSL_SPDIF2 = 106,
202 CSU_CSL_SAI2 = 107,
203 CSU_CSL_SAI3 = 108,
204 CSU_CSL_SPBA1 = 111,
205 CSU_CSL_CAAM = 114,
206 CSU_CSL_OCRAM = 118,
207 CSU_CSL_OCRAM_S = 119,
208};
209
210#endif /* IMX_SEC_DEF_H */