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git01.mediatek.com / filogic / atf / 3e8c7ec6bb320053a0b7abde981119649ac316c2 / . / plat / rockchip / rk3288 / drivers / pmu / pmu.h
blob: 06d552837ba65988d59393830ca319cc629dda2d [file] [log] [blame]
Heiko Stuebner87b9a3c2019-03-14 22:12:04 +0100[diff] [blame]1/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PMU_H
8#define PMU_H
9
10/* Allocate sp reginon in pmusram */
11#define PSRAM_SP_SIZE 0x80
12#define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE)
13
14/*****************************************************************************
15 * pmu con,reg
16 *****************************************************************************/
17#define PMU_WAKEUP_CFG0 0x0
18#define PMU_WAKEUP_CFG1 0x4
19#define PMU_PWRDN_CON 0x8
20#define PMU_PWRDN_ST 0xc
21
22#define PMU_PWRMODE_CON 0x18
23#define PMU_BUS_IDE_REQ 0x10
24#define PMU_BUS_IDE_ST 0x14
25
26#define PMU_OSC_CNT 0x20
27#define PMU_PLL_CNT 0x24
28#define PMU_STABL_CNT 0x28
29#define PMU_DDRIO0_PWR_CNT 0x2c
30#define PMU_DDRIO1_PWR_CNT 0x30
31#define PMU_WKUPRST_CNT 0x44
32#define PMU_SFT_CON 0x48
33#define PMU_PWRMODE_CON1 0x90
34
35enum pmu_pdid {
36 PD_CPU0 = 0,
37 PD_CPU1,
38 PD_CPU2,
39 PD_CPU3,
40 PD_BUS = 5,
41 PD_PERI,
42 PD_VIO,
43 PD_VIDEO,
44 PD_GPU,
45 PD_SCU = 11,
46 PD_HEVC = 14,
47 PD_END
48};
49
50enum pmu_bus_ide {
51 bus_ide_req_bus = 0,
52 bus_ide_req_peri,
53 bus_ide_req_gpu,
54 bus_ide_req_video,
55 bus_ide_req_vio,
56 bus_ide_req_core,
57 bus_ide_req_alive,
58 bus_ide_req_dma,
59 bus_ide_req_cpup,
60 bus_ide_req_hevc,
61 bus_ide_req_end
62};
63
64enum pmu_pwrmode {
65 pmu_mode_en = 0,
66 pmu_mode_core_src_gt,
67 pmu_mode_glb_int_dis,
68 pmu_mode_l2_flush_en,
69 pmu_mode_bus_pd,
70 pmu_mode_cpu0_pd,
71 pmu_mode_scu_pd,
72 pmu_mode_pll_pd = 7,
73 pmu_mode_chip_pd,
74 pmu_mode_pwr_off_comb,
75 pmu_mode_pmu_alive_use_lf,
76 pmu_mode_pmu_use_lf,
77 pmu_mode_osc_dis = 12,
78 pmu_mode_input_clamp,
79 pmu_mode_wkup_rst,
80 pmu_mode_sref0_enter,
81 pmu_mode_sref1_enter,
82 pmu_mode_ddrio0_ret,
83 pmu_mode_ddrio1_ret,
84 pmu_mode_ddrc0_gt,
85 pmu_mode_ddrc1_gt,
86 pmu_mode_ddrio0_ret_deq,
87 pmu_mode_ddrio1_ret_deq,
88};
89
90enum pmu_pwrmode1 {
91 pmu_mode_clr_bus = 0,
92 pmu_mode_clr_core,
93 pmu_mode_clr_cpup,
94 pmu_mode_clr_alive,
95 pmu_mode_clr_dma,
96 pmu_mode_clr_peri,
97 pmu_mode_clr_gpu,
98 pmu_mode_clr_video,
99 pmu_mode_clr_hevc,
100 pmu_mode_clr_vio
101};
102
103enum pmu_sft_con {
104 pmu_sft_ddrio0_ret_cfg = 6,
105 pmu_sft_ddrio1_ret_cfg = 9,
106 pmu_sft_l2flsh = 15,
107};
108
109enum pmu_wakeup_cfg1 {
110 pmu_armint_wakeup_en = 0,
111 pmu_gpio_wakeup_negedge,
112 pmu_sdmmc0_wakeup_en,
113 pmu_gpioint_wakeup_en,
114};
115
116enum pmu_bus_idle_st {
117 pmu_idle_bus = 0,
118 pmu_idle_peri,
119 pmu_idle_gpu,
120 pmu_idle_video,
121 pmu_idle_vio,
122 pmu_idle_core,
123 pmu_idle_alive,
124 pmu_idle_dma,
125 pmu_idle_cpup,
126 pmu_idle_hevc,
127 pmu_idle_ack_bus = 16,
128 pmu_idle_ack_peri,
129 pmu_idle_ack_gpu,
130 pmu_idle_ack_video,
131 pmu_idle_ack_vio,
132 pmu_idle_ack_core,
133 pmu_idle_ack_alive,
134 pmu_idle_ack_dma,
135 pmu_idle_ack_cpup,
136 pmu_idle_ack_hevc,
137};
138
139#define CHECK_CPU_WFIE_BASE (0)
140
141#define clstl_cpu_wfe -1
142#define clstb_cpu_wfe -1
143#define CKECK_WFEI_MSK 0
144
145
146#define PD_CTR_LOOP 500
147#define CHK_CPU_LOOP 500
148
149#define MAX_WAIT_CONUT 1000
150
151#endif /* PMU_H */