| Sieu Mun Tang | 8881ad0 | 2022-03-07 12:04:59 +0800 | [diff] [blame] | 1 | /* |
| Sieu Mun Tang | a544da1 | 2022-02-28 15:24:59 +0800 | [diff] [blame] | 2 | * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. |
| Sieu Mun Tang | 8881ad0 | 2022-03-07 12:04:59 +0800 | [diff] [blame] | 3 | * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #ifndef PLAT_SOCFPGA_DEF_H |
| 9 | #define PLAT_SOCFPGA_DEF_H |
| 10 | |
| 11 | #include <platform_def.h> |
| 12 | |
| 13 | /* Platform Setting */ |
| 14 | #define PLATFORM_MODEL PLAT_SOCFPGA_N5X |
| 15 | #define BOOT_SOURCE BOOT_SOURCE_SDMMC |
| 16 | |
| Sieu Mun Tang | a544da1 | 2022-02-28 15:24:59 +0800 | [diff] [blame] | 17 | /* FPGA config helpers */ |
| 18 | #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 |
| 19 | #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 |
| 20 | |
| Sieu Mun Tang | 8881ad0 | 2022-03-07 12:04:59 +0800 | [diff] [blame] | 21 | /* Register Mapping */ |
| 22 | #define SOCFPGA_MMC_REG_BASE U(0xff808000) |
| 23 | |
| 24 | #define SOCFPGA_RSTMGR_REG_BASE U(0xffd11000) |
| 25 | #define SOCFPGA_SYSMGR_REG_BASE U(0xffd12000) |
| 26 | |
| 27 | #define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000) |
| 28 | #define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100) |
| 29 | #define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200) |
| 30 | #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300) |
| 31 | |
| 32 | #endif /* PLAT_SOCFPGA_DEF_H */ |