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Masahisa Kojima099064b2020-06-11 21:46:44 +09001/* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright (c) 2020, Linaro Limited and Contributors. All rights reserved.
4 */
5
Masahisa Kojima7e917dc2020-09-23 16:52:59 +09006#include <libfdt.h>
7
Masahisa Kojima099064b2020-06-11 21:46:44 +09008#include <bl31/ehf.h>
Masahisa Kojima7e917dc2020-09-23 16:52:59 +09009#include <common/debug.h>
10#include <common/fdt_fixup.h>
11#include <common/fdt_wrappers.h>
Marcin Juszkiewicz5cc9d312023-11-08 11:07:12 +010012#include <lib/xlat_tables/xlat_tables_v2.h>
Masahisa Kojima099064b2020-06-11 21:46:44 +090013#include <services/spm_mm_partition.h>
14
15#include <platform_def.h>
16
17/* Region equivalent to MAP_DEVICE1 suitable for mapping at EL0 */
18#define MAP_DEVICE1_EL0 MAP_REGION_FLAT(DEVICE1_BASE, \
19 DEVICE1_SIZE, \
20 MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
21
Masahisa Kojima7e917dc2020-09-23 16:52:59 +090022mmap_region_t plat_qemu_secure_partition_mmap[] = {
23 QEMU_SP_IMAGE_NS_BUF_MMAP, /* must be placed at first entry */
24 MAP_DEVICE1_EL0, /* for the UART */
Masahisa Kojima099064b2020-06-11 21:46:44 +090025 QEMU_SP_IMAGE_MMAP,
26 QEMU_SPM_BUF_EL0_MMAP,
Masahisa Kojima099064b2020-06-11 21:46:44 +090027 QEMU_SP_IMAGE_RW_MMAP,
Masahisa Kojima7e917dc2020-09-23 16:52:59 +090028 MAP_SECURE_VARSTORE,
Masahisa Kojima099064b2020-06-11 21:46:44 +090029 {0}
30};
31
Masahisa Kojima617f7492021-02-02 16:00:27 +090032/* Boot information passed to a secure partition during initialisation. */
33static spm_mm_mp_info_t sp_mp_info[PLATFORM_CORE_COUNT];
Masahisa Kojima099064b2020-06-11 21:46:44 +090034
Masahisa Kojima7e917dc2020-09-23 16:52:59 +090035spm_mm_boot_info_t plat_qemu_secure_partition_boot_info = {
Masahisa Kojima099064b2020-06-11 21:46:44 +090036 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
37 .h.version = VERSION_1,
38 .h.size = sizeof(spm_mm_boot_info_t),
39 .h.attr = 0,
40 .sp_mem_base = PLAT_QEMU_SP_IMAGE_BASE,
41 .sp_mem_limit = BL32_LIMIT,
42 .sp_image_base = PLAT_QEMU_SP_IMAGE_BASE,
43 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
44 .sp_heap_base = PLAT_QEMU_SP_IMAGE_HEAP_BASE,
45 .sp_ns_comm_buf_base = PLAT_QEMU_SP_IMAGE_NS_BUF_BASE,
46 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
47 .sp_image_size = PLAT_QEMU_SP_IMAGE_SIZE,
48 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
49 .sp_heap_size = PLAT_QEMU_SP_IMAGE_HEAP_SIZE,
50 .sp_ns_comm_buf_size = PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE,
51 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
52 .num_sp_mem_regions = PLAT_QEMU_SP_IMAGE_NUM_MEM_REGIONS,
53 .num_cpus = PLATFORM_CORE_COUNT,
54 .mp_info = sp_mp_info
55};
56
57/* Enumeration of priority levels on QEMU platforms. */
58ehf_pri_desc_t qemu_exceptions[] = {
59 EHF_PRI_DESC(QEMU_PRI_BITS, PLAT_SP_PRI)
60};
61
Masahisa Kojima617f7492021-02-02 16:00:27 +090062static void qemu_initialize_mp_info(spm_mm_mp_info_t *mp_info)
63{
64 unsigned int i, j;
65 spm_mm_mp_info_t *tmp = mp_info;
66
67 for (i = 0; i < PLATFORM_CLUSTER_COUNT; i++) {
68 for (j = 0; j < PLATFORM_MAX_CPUS_PER_CLUSTER; j++) {
69 tmp->mpidr = (0x80000000 | (i << MPIDR_AFF1_SHIFT)) + j;
70 /*
71 * Linear indices and flags will be filled
72 * in the spm_mm service.
73 */
74 tmp->linear_id = 0;
75 tmp->flags = 0;
76 tmp++;
77 }
78 }
79}
80
Masahisa Kojima7e917dc2020-09-23 16:52:59 +090081int dt_add_ns_buf_node(uintptr_t *base)
82{
83 uintptr_t addr;
84 size_t size;
85 uintptr_t ns_buf_addr;
86 int node;
87 int err;
88 void *fdt = (void *)ARM_PRELOADED_DTB_BASE;
89
90 err = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE);
91 if (err < 0) {
92 ERROR("Invalid Device Tree at %p: error %d\n", fdt, err);
93 return err;
94 }
95
96 /*
97 * reserved-memory for standaloneMM non-secure buffer
98 * is allocated at the top of the first system memory region.
99 */
100 node = fdt_path_offset(fdt, "/memory");
101
102 err = fdt_get_reg_props_by_index(fdt, node, 0, &addr, &size);
103 if (err < 0) {
104 ERROR("Failed to get the memory node information\n");
105 return err;
106 }
107 INFO("System RAM @ 0x%lx - 0x%lx\n", addr, addr + size - 1);
108
109 ns_buf_addr = addr + (size - PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE);
110 INFO("reserved-memory for spm-mm @ 0x%lx - 0x%llx\n", ns_buf_addr,
111 ns_buf_addr + PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE - 1);
112
113 err = fdt_add_reserved_memory(fdt, "ns-buf-spm-mm", ns_buf_addr,
114 PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE);
115 if (err < 0) {
116 ERROR("Failed to add the reserved-memory node\n");
117 return err;
118 }
119
120 *base = ns_buf_addr;
121 return 0;
122}
123
Masahisa Kojima099064b2020-06-11 21:46:44 +0900124/* Plug in QEMU exceptions to Exception Handling Framework. */
125EHF_REGISTER_PRIORITIES(qemu_exceptions, ARRAY_SIZE(qemu_exceptions),
126 QEMU_PRI_BITS);
127
128const mmap_region_t *plat_get_secure_partition_mmap(void *cookie)
129{
Masahisa Kojima7e917dc2020-09-23 16:52:59 +0900130 uintptr_t ns_buf_base;
131
132 dt_add_ns_buf_node(&ns_buf_base);
133
134 plat_qemu_secure_partition_mmap[0].base_pa = ns_buf_base;
135 plat_qemu_secure_partition_mmap[0].base_va = ns_buf_base;
136 plat_qemu_secure_partition_boot_info.sp_ns_comm_buf_base = ns_buf_base;
137
Masahisa Kojima099064b2020-06-11 21:46:44 +0900138 return plat_qemu_secure_partition_mmap;
139}
140
141const spm_mm_boot_info_t *
142plat_get_secure_partition_boot_info(void *cookie)
143{
Masahisa Kojima617f7492021-02-02 16:00:27 +0900144 qemu_initialize_mp_info(sp_mp_info);
145
Masahisa Kojima099064b2020-06-11 21:46:44 +0900146 return &plat_qemu_secure_partition_boot_info;
147}