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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Joel Hutton5cc3bc82018-03-21 11:40:57 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6#ifndef __COMMON_DEF_H__
7#define __COMMON_DEF_H__
8
Yatharth Kochara65be2f2015-10-09 18:06:13 +01009#include <bl_common.h>
10#include <platform_def.h>
11
Dan Handley9df48042015-03-19 18:58:55 +000012/******************************************************************************
13 * Required platform porting definitions that are expected to be common to
14 * all platforms
15 *****************************************************************************/
16
17/*
18 * Platform binary types for linking
19 */
Yatharth Kocharf528faf2016-06-28 16:58:26 +010020#ifdef AARCH32
21#define PLATFORM_LINKER_FORMAT "elf32-littlearm"
22#define PLATFORM_LINKER_ARCH arm
23#else
Dan Handley9df48042015-03-19 18:58:55 +000024#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
25#define PLATFORM_LINKER_ARCH aarch64
Yatharth Kocharf528faf2016-06-28 16:58:26 +010026#endif /* AARCH32 */
Dan Handley9df48042015-03-19 18:58:55 +000027
28/*
29 * Generic platform constants
30 */
31#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
32
Yatharth Kochar51f76f62016-09-12 16:10:33 +010033#if LOAD_IMAGE_V2
Yatharth Kochara65be2f2015-10-09 18:06:13 +010034#define BL2_IMAGE_DESC { \
35 .image_id = BL2_IMAGE_ID, \
Yatharth Kocharf11b29a2016-02-01 11:04:46 +000036 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \
Yatharth Kochar51f76f62016-09-12 16:10:33 +010037 VERSION_2, image_info_t, 0), \
38 .image_info.image_base = BL2_BASE, \
39 .image_info.image_max_size = BL2_LIMIT - BL2_BASE,\
40 SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, \
41 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),\
42 .ep_info.pc = BL2_BASE, \
43}
44#else /* LOAD_IMAGE_V2 */
45#define BL2_IMAGE_DESC { \
46 .image_id = BL2_IMAGE_ID, \
47 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \
Yatharth Kocharf11b29a2016-02-01 11:04:46 +000048 VERSION_1, image_info_t, 0), \
Yatharth Kochara65be2f2015-10-09 18:06:13 +010049 .image_info.image_base = BL2_BASE, \
Yatharth Kocharf11b29a2016-02-01 11:04:46 +000050 SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, \
51 VERSION_1, entry_point_info_t, SECURE | EXECUTABLE),\
52 .ep_info.pc = BL2_BASE, \
Yatharth Kochara65be2f2015-10-09 18:06:13 +010053}
Yatharth Kochar51f76f62016-09-12 16:10:33 +010054#endif /* LOAD_IMAGE_V2 */
Yatharth Kochara65be2f2015-10-09 18:06:13 +010055
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010056/*
57 * The following constants identify the extents of the code & read-only data
58 * regions. These addresses are used by the MMU setup code and therefore they
59 * must be page-aligned.
60 *
61 * When the code and read-only data are mapped as a single atomic section
62 * (i.e. when SEPARATE_CODE_AND_RODATA=0) then we treat the whole section as
63 * code by specifying the read-only data section as empty.
64 *
65 * BL1 is different than the other images in the sense that its read-write data
66 * originally lives in Trusted ROM and needs to be relocated in Trusted SRAM at
67 * run-time. Therefore, the read-write data in ROM can be mapped with the same
68 * memory attributes as the read-only data region. For this reason, BL1 uses
69 * different macros.
70 *
71 * Note that BL1_ROM_END is not necessarily aligned on a page boundary as it
72 * just points to the end of BL1's actual content in Trusted ROM. Therefore it
73 * needs to be rounded up to the next page size in order to map the whole last
74 * page of it with the right memory attributes.
75 */
76#if SEPARATE_CODE_AND_RODATA
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010077
Masahiro Yamada51bef612017-01-18 02:10:08 +090078#define BL1_CODE_END BL_CODE_END
Joel Hutton5cc3bc82018-03-21 11:40:57 +000079#define BL1_RO_DATA_BASE BL_RO_DATA_BASE
Masahiro Yamada51bef612017-01-18 02:10:08 +090080#define BL1_RO_DATA_END round_up(BL1_ROM_END, PAGE_SIZE)
Jiafei Pan43a7bf42018-03-21 07:20:09 +000081#if BL2_IN_XIP_MEM
82#define BL2_CODE_END BL_CODE_END
83#define BL2_RO_DATA_BASE BL_RO_DATA_BASE
84#define BL2_RO_DATA_END round_up(BL2_ROM_END, PAGE_SIZE)
85#endif /* BL2_IN_XIP_MEM */
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010086#else
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010087#define BL_RO_DATA_BASE 0
Masahiro Yamada51bef612017-01-18 02:10:08 +090088#define BL_RO_DATA_END 0
Masahiro Yamada51bef612017-01-18 02:10:08 +090089#define BL1_CODE_END round_up(BL1_ROM_END, PAGE_SIZE)
Jiafei Pan43a7bf42018-03-21 07:20:09 +000090#if BL2_IN_XIP_MEM
91#define BL2_RO_DATA_BASE 0
92#define BL2_RO_DATA_END 0
93#define BL2_CODE_END round_up(BL2_ROM_END, PAGE_SIZE)
94#endif /* BL2_IN_XIP_MEM */
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010095#endif /* SEPARATE_CODE_AND_RODATA */
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010096#endif /* __COMMON_DEF_H__ */