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Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00001/*
Remi Pommareldb289172019-04-04 23:12:56 +02002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef GXBB_DEF_H
8#define GXBB_DEF_H
9
10#include <lib/utils_def.h>
11
12/*******************************************************************************
13 * System oscillator
14 ******************************************************************************/
15#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */
16
17/*******************************************************************************
18 * Memory regions
19 ******************************************************************************/
20#define GXBB_NSDRAM0_BASE UL(0x01000000)
21#define GXBB_NSDRAM0_SIZE UL(0x0F000000)
22
23#define GXBB_NSDRAM1_BASE UL(0x10000000)
24#define GXBB_NSDRAM1_SIZE UL(0x00100000)
25
26#define BL31_BASE UL(0x05100000)
27#define BL31_SIZE UL(0x000C0000)
28#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
29
30/* Shared memory used for SMC services */
31#define GXBB_SHARE_MEM_INPUT_BASE UL(0x050FE000)
32#define GXBB_SHARE_MEM_OUTPUT_BASE UL(0x050FF000)
33
34#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000)
35#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000)
36
37#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000)
38#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000)
39
40#define GXBB_TZRAM_BASE UL(0xD9000000)
41#define GXBB_TZRAM_SIZE UL(0x00014000)
42/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
43
44/* Mailboxes */
45#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800)
46#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00)
47#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00)
48
49// * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3)
50// * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) *
51// * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) *
52
53#define GXBB_TZROM_BASE UL(0xD9040000)
54#define GXBB_TZROM_SIZE UL(0x00010000)
55
56#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000)
57#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000)
58
59#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000)
60#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000)
61
62/*******************************************************************************
63 * GIC-400 and interrupt handling related constants
64 ******************************************************************************/
65#define GXBB_GICD_BASE UL(0xC4301000)
66#define GXBB_GICC_BASE UL(0xC4302000)
67
68#define IRQ_SEC_PHY_TIMER 29
69
70#define IRQ_SEC_SGI_0 8
71#define IRQ_SEC_SGI_1 9
72#define IRQ_SEC_SGI_2 10
73#define IRQ_SEC_SGI_3 11
74#define IRQ_SEC_SGI_4 12
75#define IRQ_SEC_SGI_5 13
76#define IRQ_SEC_SGI_6 14
77#define IRQ_SEC_SGI_7 15
78
79/*******************************************************************************
80 * UART definitions
81 ******************************************************************************/
82#define GXBB_UART0_AO_BASE UL(0xC81004C0)
83#define GXBB_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ
84#define GXBB_UART_BAUDRATE U(115200)
85
86/*******************************************************************************
87 * Memory-mapped I/O Registers
88 ******************************************************************************/
89#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4)
90
91#define GXBB_SYS_CPU_CFG7 UL(0xC8834664)
92
93#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C)
Remi Pommareldb289172019-04-04 23:12:56 +020094#define GXBB_AO_RTI_SCP_STAT UL(0xDA10023C)
95#define GXBB_AO_RTI_SCP_READY_OFF U(0x14)
96#define GXBB_A0_RTI_SCP_READY_MASK U(3)
97#define GXBB_AO_RTI_SCP_IS_READY(v) \
98 ((((v) >> GXBB_AO_RTI_SCP_READY_OFF) & \
99 GXBB_A0_RTI_SCP_READY_MASK) == GXBB_A0_RTI_SCP_READY_MASK)
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +0000100
101#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404)
102#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
103#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C)
104#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428)
105#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C)
106#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430)
107
108/*******************************************************************************
109 * System Monitor Call IDs and arguments
110 ******************************************************************************/
111#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020)
112#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021)
113
114#define GXBB_SM_EFUSE_READ U(0x82000030)
115#define GXBB_SM_EFUSE_USER_MAX U(0x82000033)
116
117#define GXBB_SM_JTAG_ON U(0x82000040)
118#define GXBB_SM_JTAG_OFF U(0x82000041)
119
120#define GXBB_JTAG_STATE_ON U(0)
121#define GXBB_JTAG_STATE_OFF U(1)
122
123#define GXBB_JTAG_M3_AO U(0)
124#define GXBB_JTAG_M3_EE U(1)
125#define GXBB_JTAG_A53_AO U(2)
126#define GXBB_JTAG_A53_EE U(3)
127
128#endif /* GXBB_DEF_H */