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Joel Huttona7c46872018-01-10 16:06:07 +00001/*
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +00002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Joel Huttona7c46872018-01-10 16:06:07 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef CORTEX_HELIOS_H
8#define CORTEX_HELIOS_H
Joel Huttona7c46872018-01-10 16:06:07 +00009
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +000010#include <lib/utils_def.h>
11
Joel Huttona7c46872018-01-10 16:06:07 +000012#define CORTEX_HELIOS_MIDR U(0x410FD060)
13
14/*******************************************************************************
15 * CPU Extended Control register specific definitions.
16 ******************************************************************************/
17#define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4
18
19/*******************************************************************************
20 * CPU Auxiliary Control register specific definitions.
21 ******************************************************************************/
22#define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0
23
24/*******************************************************************************
25 * CPU Power Control register specific definitions.
26 ******************************************************************************/
27
28#define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7
29#define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
30
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000031#endif /* CORTEX_HELIOS_H */