Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 31 | #include <arch.h> |
| 32 | #include <arch_helpers.h> |
Varun Wadekar | a64806a | 2016-01-05 15:17:41 -0800 | [diff] [blame] | 33 | #include <assert.h> |
| 34 | #include <bl_common.h> |
| 35 | #include <context.h> |
| 36 | #include <context_mgmt.h> |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 37 | #include <debug.h> |
Varun Wadekar | 8964509 | 2016-02-09 14:55:44 -0800 | [diff] [blame] | 38 | #include <denver.h> |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 39 | #include <mce.h> |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 40 | #include <psci.h> |
Varun Wadekar | 782c83d | 2017-03-14 14:25:35 -0700 | [diff] [blame] | 41 | #include <t18x_ari.h> |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 42 | #include <tegra_private.h> |
| 43 | |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 44 | extern void prepare_cpu_pwr_dwn(void); |
| 45 | |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 46 | /* state id mask */ |
| 47 | #define TEGRA186_STATE_ID_MASK 0xF |
| 48 | /* constants to get power state's wake time */ |
| 49 | #define TEGRA186_WAKE_TIME_MASK 0xFFFFFF |
| 50 | #define TEGRA186_WAKE_TIME_SHIFT 4 |
| 51 | |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 52 | static unsigned int wake_time[PLATFORM_CORE_COUNT]; |
| 53 | |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 54 | /* System power down state */ |
| 55 | uint32_t tegra186_system_powerdn_state = TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF; |
| 56 | |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 57 | int32_t tegra_soc_validate_power_state(unsigned int power_state, |
| 58 | psci_power_state_t *req_state) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 59 | { |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 60 | int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; |
| 61 | int cpu = read_mpidr() & MPIDR_CPU_MASK; |
Varun Wadekar | 8964509 | 2016-02-09 14:55:44 -0800 | [diff] [blame] | 62 | int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 63 | |
Varun Wadekar | 8964509 | 2016-02-09 14:55:44 -0800 | [diff] [blame] | 64 | if (impl == DENVER_IMPL) |
| 65 | cpu |= 0x4; |
| 66 | |
| 67 | wake_time[cpu] = (power_state >> TEGRA186_WAKE_TIME_SHIFT) & |
| 68 | TEGRA186_WAKE_TIME_MASK; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 69 | |
| 70 | /* Sanity check the requested state id */ |
| 71 | switch (state_id) { |
| 72 | case PSTATE_ID_CORE_IDLE: |
| 73 | case PSTATE_ID_CORE_POWERDN: |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 74 | /* |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 75 | * Core powerdown request only for afflvl 0 |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 76 | */ |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 77 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; |
| 78 | |
| 79 | break; |
| 80 | |
| 81 | default: |
| 82 | ERROR("%s: unsupported state id (%d)\n", __func__, state_id); |
| 83 | return PSCI_E_INVALID_PARAMS; |
| 84 | } |
| 85 | |
| 86 | return PSCI_E_SUCCESS; |
| 87 | } |
| 88 | |
| 89 | int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
| 90 | { |
| 91 | const plat_local_state_t *pwr_domain_state; |
| 92 | unsigned int stateid_afflvl0; |
| 93 | int cpu = read_mpidr() & MPIDR_CPU_MASK; |
Varun Wadekar | 8964509 | 2016-02-09 14:55:44 -0800 | [diff] [blame] | 94 | int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; |
| 95 | |
| 96 | if (impl == DENVER_IMPL) |
| 97 | cpu |= 0x4; |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 98 | |
| 99 | /* get the state ID */ |
| 100 | pwr_domain_state = target_state->pwr_domain_state; |
| 101 | stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & |
| 102 | TEGRA186_STATE_ID_MASK; |
| 103 | |
| 104 | if (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) { |
| 105 | |
| 106 | /* Prepare for cpu idle */ |
| 107 | (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, |
| 108 | TEGRA_ARI_CORE_C6, wake_time[cpu], 0); |
| 109 | |
| 110 | } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { |
| 111 | |
| 112 | /* Prepare for cpu powerdn */ |
| 113 | (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, |
| 114 | TEGRA_ARI_CORE_C7, wake_time[cpu], 0); |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 115 | |
Varun Wadekar | 4223657 | 2016-01-18 19:03:19 -0800 | [diff] [blame] | 116 | } else { |
| 117 | ERROR("%s: Unknown state id\n", __func__); |
| 118 | return PSCI_E_NOT_SUPPORTED; |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | return PSCI_E_SUCCESS; |
| 122 | } |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 123 | |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 124 | int tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 125 | { |
| 126 | int target_cpu = mpidr & MPIDR_CPU_MASK; |
| 127 | int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> |
| 128 | MPIDR_AFFINITY_BITS; |
| 129 | |
| 130 | if (target_cluster > MPIDR_AFFLVL1) { |
| 131 | ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr); |
| 132 | return PSCI_E_NOT_PRESENT; |
| 133 | } |
| 134 | |
| 135 | /* construct the target CPU # */ |
| 136 | target_cpu |= (target_cluster << 2); |
| 137 | |
| 138 | mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); |
| 139 | |
| 140 | return PSCI_E_SUCCESS; |
| 141 | } |
| 142 | |
Varun Wadekar | c2c3a2a | 2016-01-08 17:38:51 -0800 | [diff] [blame] | 143 | int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 144 | { |
Varun Wadekar | a64806a | 2016-01-05 15:17:41 -0800 | [diff] [blame] | 145 | cpu_context_t *ctx = cm_get_context(NON_SECURE); |
| 146 | gp_regs_t *gp_regs = get_gpregs_ctx(ctx); |
Varun Wadekar | e26a55a | 2016-02-26 11:09:21 -0800 | [diff] [blame] | 147 | int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; |
Varun Wadekar | a64806a | 2016-01-05 15:17:41 -0800 | [diff] [blame] | 148 | |
| 149 | assert(ctx); |
| 150 | assert(gp_regs); |
| 151 | |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 152 | /* Turn off wake_mask */ |
Varun Wadekar | a64806a | 2016-01-05 15:17:41 -0800 | [diff] [blame] | 153 | write_ctx_reg(gp_regs, CTX_GPREG_X4, 0); |
| 154 | write_ctx_reg(gp_regs, CTX_GPREG_X5, 0); |
| 155 | write_ctx_reg(gp_regs, CTX_GPREG_X6, 1); |
| 156 | mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, TEGRA_ARI_CLUSTER_CC7, |
| 157 | 0, TEGRA_ARI_SYSTEM_SC7); |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 158 | |
Varun Wadekar | e26a55a | 2016-02-26 11:09:21 -0800 | [diff] [blame] | 159 | /* Disable Denver's DCO operations */ |
| 160 | if (impl == DENVER_IMPL) |
| 161 | denver_disable_dco(); |
| 162 | |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 163 | /* Turn off CPU */ |
Varun Wadekar | a64806a | 2016-01-05 15:17:41 -0800 | [diff] [blame] | 164 | return mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, |
Varun Wadekar | 8964509 | 2016-02-09 14:55:44 -0800 | [diff] [blame] | 165 | MCE_CORE_SLEEP_TIME_INFINITE, 0); |
Varun Wadekar | abd153c | 2015-09-14 09:31:39 +0530 | [diff] [blame] | 166 | } |
Varun Wadekar | 782c83d | 2017-03-14 14:25:35 -0700 | [diff] [blame] | 167 | |
| 168 | __dead2 void tegra_soc_prepare_system_off(void) |
| 169 | { |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 170 | cpu_context_t *ctx = cm_get_context(NON_SECURE); |
| 171 | gp_regs_t *gp_regs = get_gpregs_ctx(ctx); |
| 172 | uint32_t val; |
| 173 | |
| 174 | if (tegra186_system_powerdn_state == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) { |
| 175 | |
| 176 | /* power off the entire system */ |
| 177 | mce_enter_ccplex_state(tegra186_system_powerdn_state); |
| 178 | |
| 179 | } else if (tegra186_system_powerdn_state == TEGRA_ARI_SYSTEM_SC8) { |
| 180 | |
| 181 | /* loop until other CPUs power down */ |
| 182 | do { |
| 183 | val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, |
| 184 | TEGRA_ARI_CORE_C7, |
| 185 | MCE_CORE_SLEEP_TIME_INFINITE, |
| 186 | 0); |
| 187 | } while (val == 0); |
| 188 | |
| 189 | /* Prepare for quasi power down */ |
| 190 | write_ctx_reg(gp_regs, CTX_GPREG_X4, 1); |
| 191 | write_ctx_reg(gp_regs, CTX_GPREG_X5, 0); |
| 192 | write_ctx_reg(gp_regs, CTX_GPREG_X6, 1); |
| 193 | (void)mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, |
| 194 | TEGRA_ARI_CLUSTER_CC7, 0, TEGRA_ARI_SYSTEM_SC8); |
| 195 | |
| 196 | /* Enter quasi power down state */ |
| 197 | (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, |
| 198 | TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); |
| 199 | |
| 200 | /* disable GICC */ |
| 201 | tegra_gic_cpuif_deactivate(); |
| 202 | |
| 203 | /* power down core */ |
| 204 | prepare_cpu_pwr_dwn(); |
| 205 | |
| 206 | } else { |
| 207 | ERROR("%s: unsupported power down state (%d)\n", __func__, |
| 208 | tegra186_system_powerdn_state); |
| 209 | } |
| 210 | |
| 211 | wfi(); |
| 212 | |
| 213 | /* wait for the system to power down */ |
| 214 | for (;;) { |
| 215 | ; |
| 216 | } |
Varun Wadekar | 782c83d | 2017-03-14 14:25:35 -0700 | [diff] [blame] | 217 | } |
Varun Wadekar | 38020c9 | 2016-01-07 14:36:12 -0800 | [diff] [blame] | 218 | |
| 219 | int tegra_soc_prepare_system_reset(void) |
| 220 | { |
| 221 | mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT); |
| 222 | |
| 223 | return PSCI_E_SUCCESS; |
| 224 | } |