Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1 | /* |
Marek Vasut | 6534b54 | 2019-06-14 02:23:04 +0200 | [diff] [blame] | 2 | * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved. |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stdint.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
| 9 | #include <common/debug.h> |
| 10 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 11 | #include "../qos_common.h" |
| 12 | #include "../qos_reg.h" |
| 13 | #include "qos_init_e3_v10.h" |
| 14 | |
Marek Vasut | 48cc693 | 2018-12-12 16:35:00 +0100 | [diff] [blame] | 15 | #define RCAR_QOS_VERSION "rev.0.05" |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 16 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 17 | #define REF_ARS_ARBSTOPCYCLE_E3 (((SL_INIT_SSLOTCLK_E3) - 5U) << 16U) |
| 18 | |
| 19 | #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT |
| 20 | |
| 21 | #if RCAR_REF_INT == RCAR_REF_DEFAULT |
| 22 | #include "qos_init_e3_v10_mstat390.h" |
| 23 | #else |
| 24 | #include "qos_init_e3_v10_mstat780.h" |
| 25 | #endif |
| 26 | |
| 27 | #endif |
| 28 | |
Marek Vasut | 9fdcbd4 | 2019-06-14 15:50:57 +0200 | [diff] [blame] | 29 | struct rcar_gen3_dbsc_qos_settings e3_qos[] = { |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 30 | /* BUFCAM settings */ |
Marek Vasut | 9fdcbd4 | 2019-06-14 15:50:57 +0200 | [diff] [blame] | 31 | { DBSC_DBCAM0CNF1, 0x00043218 }, |
| 32 | { DBSC_DBCAM0CNF2, 0x000000F4 }, |
| 33 | { DBSC_DBSCHCNT0, 0x000F0037 }, |
| 34 | { DBSC_DBSCHSZ0, 0x00000001 }, |
| 35 | { DBSC_DBSCHRW0, 0x22421111 }, |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 36 | |
| 37 | /* DDR3 */ |
Marek Vasut | 9fdcbd4 | 2019-06-14 15:50:57 +0200 | [diff] [blame] | 38 | { DBSC_SCFCTST2, 0x012F1123 }, |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 39 | |
| 40 | /* QoS Settings */ |
Marek Vasut | 9fdcbd4 | 2019-06-14 15:50:57 +0200 | [diff] [blame] | 41 | { DBSC_DBSCHQOS00, 0x00000F00 }, |
| 42 | { DBSC_DBSCHQOS01, 0x00000B00 }, |
| 43 | { DBSC_DBSCHQOS02, 0x00000000 }, |
| 44 | { DBSC_DBSCHQOS03, 0x00000000 }, |
| 45 | { DBSC_DBSCHQOS40, 0x00000300 }, |
| 46 | { DBSC_DBSCHQOS41, 0x000002F0 }, |
| 47 | { DBSC_DBSCHQOS42, 0x00000200 }, |
| 48 | { DBSC_DBSCHQOS43, 0x00000100 }, |
| 49 | { DBSC_DBSCHQOS90, 0x00000100 }, |
| 50 | { DBSC_DBSCHQOS91, 0x000000F0 }, |
| 51 | { DBSC_DBSCHQOS92, 0x000000A0 }, |
| 52 | { DBSC_DBSCHQOS93, 0x00000040 }, |
| 53 | { DBSC_DBSCHQOS130, 0x00000100 }, |
| 54 | { DBSC_DBSCHQOS131, 0x000000F0 }, |
| 55 | { DBSC_DBSCHQOS132, 0x000000A0 }, |
| 56 | { DBSC_DBSCHQOS133, 0x00000040 }, |
| 57 | { DBSC_DBSCHQOS140, 0x000000C0 }, |
| 58 | { DBSC_DBSCHQOS141, 0x000000B0 }, |
| 59 | { DBSC_DBSCHQOS142, 0x00000080 }, |
| 60 | { DBSC_DBSCHQOS143, 0x00000040 }, |
| 61 | { DBSC_DBSCHQOS150, 0x00000040 }, |
| 62 | { DBSC_DBSCHQOS151, 0x00000030 }, |
| 63 | { DBSC_DBSCHQOS152, 0x00000020 }, |
| 64 | { DBSC_DBSCHQOS153, 0x00000010 }, |
| 65 | }; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 66 | |
| 67 | void qos_init_e3_v10(void) |
| 68 | { |
Marek Vasut | 9fdcbd4 | 2019-06-14 15:50:57 +0200 | [diff] [blame] | 69 | rcar_qos_dbsc_setting(e3_qos, ARRAY_SIZE(e3_qos), true); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 70 | |
| 71 | /* DRAM Split Address mapping */ |
| 72 | #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH |
| 73 | #if RCAR_LSI == RCAR_E3 |
| 74 | #error "Don't set DRAM Split 4ch(E3)" |
| 75 | #else |
| 76 | ERROR("DRAM Split 4ch not supported.(E3)"); |
| 77 | panic(); |
| 78 | #endif |
| 79 | #elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) |
| 80 | #if RCAR_LSI == RCAR_E3 |
| 81 | #error "Don't set DRAM Split 2ch(E3)" |
| 82 | #else |
| 83 | ERROR("DRAM Split 2ch not supported.(E3)"); |
| 84 | panic(); |
| 85 | #endif |
| 86 | #else |
| 87 | NOTICE("BL2: DRAM Split is OFF\n"); |
| 88 | #endif |
| 89 | |
| 90 | #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) |
| 91 | #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT |
| 92 | NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); |
| 93 | #endif |
| 94 | |
| 95 | #if RCAR_REF_INT == RCAR_REF_DEFAULT |
| 96 | NOTICE("BL2: DRAM refresh interval 3.9 usec\n"); |
| 97 | #else |
| 98 | NOTICE("BL2: DRAM refresh interval 7.8 usec\n"); |
| 99 | #endif |
| 100 | |
| 101 | io_write_32(QOSCTRL_RAS, 0x00000020U); |
| 102 | io_write_64(QOSCTRL_DANN, 0x0404020002020201UL); |
| 103 | io_write_32(QOSCTRL_DANT, 0x00100804U); |
| 104 | io_write_32(QOSCTRL_FSS, 0x0000000AU); |
| 105 | io_write_32(QOSCTRL_INSFC, 0x06330001U); |
| 106 | io_write_32(QOSCTRL_EARLYR, 0x00000000U); |
| 107 | io_write_32(QOSCTRL_RACNT0, 0x00010003U); |
| 108 | |
| 109 | io_write_32(QOSCTRL_SL_INIT, |
| 110 | SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | |
| 111 | SL_INIT_SSLOTCLK_E3); |
| 112 | io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_E3); |
| 113 | |
Marek Vasut | d551d12 | 2019-06-14 01:04:07 +0200 | [diff] [blame] | 114 | /* QOSBW SRAM setting */ |
| 115 | uint32_t i; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 116 | |
Marek Vasut | d551d12 | 2019-06-14 01:04:07 +0200 | [diff] [blame] | 117 | for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { |
| 118 | io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); |
| 119 | io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); |
| 120 | } |
| 121 | for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { |
| 122 | io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); |
| 123 | io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 124 | } |
| 125 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 126 | /* RT bus Leaf setting */ |
| 127 | io_write_32(RT_ACT0, 0x00000000U); |
| 128 | io_write_32(RT_ACT1, 0x00000000U); |
| 129 | |
| 130 | /* CCI bus Leaf setting */ |
| 131 | io_write_32(CPU_ACT0, 0x00000003U); |
| 132 | io_write_32(CPU_ACT1, 0x00000003U); |
| 133 | |
| 134 | io_write_32(QOSCTRL_RAEN, 0x00000001U); |
| 135 | |
| 136 | io_write_32(QOSCTRL_STATQC, 0x00000001U); |
| 137 | #else |
| 138 | NOTICE("BL2: QoS is None\n"); |
| 139 | |
| 140 | io_write_32(QOSCTRL_RAEN, 0x00000001U); |
| 141 | #endif |
| 142 | } |