blob: 617093345b6e1c86620ea7f995bf788174138266 [file] [log] [blame]
Achin Gupta1fa7eb62015-11-03 14:18:34 +00001/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arm_def.h>
32#include <arm_gic.h>
33#include <plat_arm.h>
34#include <platform.h>
35#include <platform_def.h>
36
37/******************************************************************************
38 * The following function is defined as weak to allow a platform to override
39 * the way the Legacy GICv3 driver is initialised and used.
40 *****************************************************************************/
41#pragma weak plat_arm_gic_driver_init
42#pragma weak plat_arm_gic_init
43#pragma weak plat_arm_gic_cpuif_enable
44#pragma weak plat_arm_gic_cpuif_disable
45#pragma weak plat_arm_gic_pcpu_init
46
47/*
48 * In the GICv3 Legacy mode, the Group 1 secure interrupts are treated as Group
49 * 0 interrupts.
50 */
51const unsigned int irq_sec_array[] = {
52 PLAT_ARM_G0_IRQS,
53 PLAT_ARM_G1S_IRQS
54};
55
56void plat_arm_gic_driver_init(void)
57{
58 arm_gic_init(PLAT_ARM_GICC_BASE,
59 PLAT_ARM_GICD_BASE,
60 PLAT_ARM_GICR_BASE,
61 irq_sec_array,
62 ARRAY_SIZE(irq_sec_array));
63}
64
65/******************************************************************************
66 * ARM common helper to initialize the GIC.
67 *****************************************************************************/
68void plat_arm_gic_init(void)
69{
70 arm_gic_setup();
71}
72
73/******************************************************************************
74 * ARM common helper to enable the GIC CPU interface
75 *****************************************************************************/
76void plat_arm_gic_cpuif_enable(void)
77{
78 arm_gic_cpuif_setup();
79}
80
81/******************************************************************************
82 * ARM common helper to disable the GIC CPU interface
83 *****************************************************************************/
84void plat_arm_gic_cpuif_disable(void)
85{
86 arm_gic_cpuif_deactivate();
87}
88
89/******************************************************************************
90 * ARM common helper to initialize the per-cpu distributor in GICv2 or
91 * redistributor interface in GICv3.
92 *****************************************************************************/
93void plat_arm_gic_pcpu_init(void)
94{
95 arm_gic_pcpu_distif_setup();
96}