Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 1 | /* |
Mario Bălănică | 3bb68ae | 2023-12-01 05:12:58 +0200 | [diff] [blame^] | 2 | * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <assert_macros.S> |
| 10 | #include <platform_def.h> |
| 11 | #include <cortex_a72.h> |
| 12 | |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 13 | .globl plat_crash_console_flush |
| 14 | .globl plat_crash_console_init |
| 15 | .globl plat_crash_console_putc |
| 16 | .globl platform_mem_init |
| 17 | .globl plat_get_my_entrypoint |
| 18 | .globl plat_is_my_cpu_primary |
| 19 | .globl plat_my_core_pos |
| 20 | .globl plat_reset_handler |
| 21 | .globl plat_rpi3_calc_core_pos |
| 22 | .globl plat_secondary_cold_boot_setup |
Andre Przywara | 98e4856 | 2020-03-12 14:20:04 +0000 | [diff] [blame] | 23 | .globl plat_rpi_get_model |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 24 | |
| 25 | /* ----------------------------------------------------- |
| 26 | * unsigned int plat_my_core_pos(void) |
| 27 | * |
| 28 | * This function uses the plat_rpi3_calc_core_pos() |
| 29 | * definition to get the index of the calling CPU. |
| 30 | * ----------------------------------------------------- |
| 31 | */ |
| 32 | func plat_my_core_pos |
| 33 | mrs x0, mpidr_el1 |
| 34 | b plat_rpi3_calc_core_pos |
| 35 | endfunc plat_my_core_pos |
| 36 | |
| 37 | /* ----------------------------------------------------- |
| 38 | * unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr); |
| 39 | * |
| 40 | * CorePos = (ClusterId * 4) + CoreId |
| 41 | * ----------------------------------------------------- |
| 42 | */ |
| 43 | func plat_rpi3_calc_core_pos |
| 44 | and x1, x0, #MPIDR_CPU_MASK |
| 45 | and x0, x0, #MPIDR_CLUSTER_MASK |
| 46 | add x0, x1, x0, LSR #6 |
| 47 | ret |
| 48 | endfunc plat_rpi3_calc_core_pos |
| 49 | |
| 50 | /* ----------------------------------------------------- |
| 51 | * unsigned int plat_is_my_cpu_primary (void); |
| 52 | * |
| 53 | * Find out whether the current cpu is the primary |
| 54 | * cpu. |
| 55 | * ----------------------------------------------------- |
| 56 | */ |
| 57 | func plat_is_my_cpu_primary |
| 58 | mrs x0, mpidr_el1 |
| 59 | and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) |
Andre Przywara | 98e4856 | 2020-03-12 14:20:04 +0000 | [diff] [blame] | 60 | cmp x0, #RPI_PRIMARY_CPU |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 61 | cset w0, eq |
| 62 | ret |
| 63 | endfunc plat_is_my_cpu_primary |
| 64 | |
| 65 | /* ----------------------------------------------------- |
Andrei Warkentin | c96d430 | 2020-03-11 22:11:06 -0700 | [diff] [blame] | 66 | * void plat_wait_for_warm_boot (void); |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 67 | * |
| 68 | * This function performs any platform specific actions |
Andrei Warkentin | c96d430 | 2020-03-11 22:11:06 -0700 | [diff] [blame] | 69 | * needed for a CPU to be put into holding pen to wait |
| 70 | * for a warm boot request. |
| 71 | * The function will never return. |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 72 | * ----------------------------------------------------- |
| 73 | */ |
Andrei Warkentin | c96d430 | 2020-03-11 22:11:06 -0700 | [diff] [blame] | 74 | func plat_wait_for_warm_boot |
| 75 | /* |
| 76 | * Calculate address of our hold entry. |
| 77 | * As the function will never return, there is no need to save LR. |
| 78 | */ |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 79 | bl plat_my_core_pos |
| 80 | lsl x0, x0, #3 |
| 81 | mov_imm x2, PLAT_RPI3_TM_HOLD_BASE |
| 82 | add x0, x0, x2 |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 83 | /* |
| 84 | * This code runs way before requesting the warmboot of this core, |
| 85 | * so it is possible to clear the mailbox before getting a request |
| 86 | * to boot. |
| 87 | */ |
| 88 | mov x1, PLAT_RPI3_TM_HOLD_STATE_WAIT |
| 89 | str x1,[x0] |
| 90 | |
| 91 | /* Wait until we have a go */ |
| 92 | poll_mailbox: |
| 93 | wfe |
| 94 | ldr x1, [x0] |
| 95 | cmp x1, PLAT_RPI3_TM_HOLD_STATE_GO |
| 96 | bne poll_mailbox |
| 97 | |
| 98 | /* Jump to the provided entrypoint */ |
| 99 | mov_imm x0, PLAT_RPI3_TM_ENTRYPOINT |
| 100 | ldr x1, [x0] |
| 101 | br x1 |
Andrei Warkentin | c96d430 | 2020-03-11 22:11:06 -0700 | [diff] [blame] | 102 | endfunc plat_wait_for_warm_boot |
| 103 | |
| 104 | /* ----------------------------------------------------- |
| 105 | * void plat_secondary_cold_boot_setup (void); |
| 106 | * |
| 107 | * This function performs any platform specific actions |
| 108 | * needed for a secondary cpu after a cold reset e.g |
| 109 | * mark the cpu's presence, mechanism to place it in a |
| 110 | * holding pen etc. |
| 111 | * ----------------------------------------------------- |
| 112 | */ |
| 113 | func plat_secondary_cold_boot_setup |
| 114 | b plat_wait_for_warm_boot |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 115 | endfunc plat_secondary_cold_boot_setup |
| 116 | |
| 117 | /* --------------------------------------------------------------------- |
| 118 | * uintptr_t plat_get_my_entrypoint (void); |
| 119 | * |
| 120 | * Main job of this routine is to distinguish between a cold and a warm |
| 121 | * boot. |
| 122 | * |
| 123 | * This functions returns: |
| 124 | * - 0 for a cold boot. |
| 125 | * - Any other value for a warm boot. |
| 126 | * --------------------------------------------------------------------- |
| 127 | */ |
| 128 | func plat_get_my_entrypoint |
Andrei Warkentin | c96d430 | 2020-03-11 22:11:06 -0700 | [diff] [blame] | 129 | mov x1, x30 |
| 130 | bl plat_is_my_cpu_primary |
| 131 | /* |
| 132 | * Secondaries always cold boot. |
| 133 | */ |
| 134 | cbz w0, 1f |
| 135 | /* |
| 136 | * Primaries warm boot if they are requested |
| 137 | * to power off. |
| 138 | */ |
| 139 | mov_imm x0, PLAT_RPI3_TM_HOLD_BASE |
| 140 | ldr x0, [x0] |
| 141 | cmp x0, PLAT_RPI3_TM_HOLD_STATE_BSP_OFF |
| 142 | adr x0, plat_wait_for_warm_boot |
| 143 | csel x0, x0, xzr, eq |
| 144 | ret x1 |
| 145 | 1: mov x0, #0 |
| 146 | ret x1 |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 147 | endfunc plat_get_my_entrypoint |
| 148 | |
| 149 | /* --------------------------------------------- |
| 150 | * void platform_mem_init (void); |
| 151 | * |
| 152 | * No need to carry out any memory initialization. |
| 153 | * --------------------------------------------- |
| 154 | */ |
| 155 | func platform_mem_init |
| 156 | ret |
| 157 | endfunc platform_mem_init |
| 158 | |
| 159 | /* --------------------------------------------- |
| 160 | * int plat_crash_console_init(void) |
| 161 | * Function to initialize the crash console |
| 162 | * without a C Runtime to print crash report. |
| 163 | * Clobber list : x0 - x3 |
| 164 | * --------------------------------------------- |
| 165 | */ |
| 166 | func plat_crash_console_init |
Mario Bălănică | 3bb68ae | 2023-12-01 05:12:58 +0200 | [diff] [blame^] | 167 | mov_imm x0, PLAT_RPI_CRASH_UART_BASE |
| 168 | #if PLAT_RPI_CRASH_UART_BASE == PLAT_RPI_PL011_UART_BASE |
| 169 | mov_imm x1, RPI4_PL011_UART_CLOCK |
| 170 | mov_imm x2, PLAT_RPI_UART_BAUDRATE |
| 171 | b console_pl011_core_init |
| 172 | #else |
Andre Przywara | eb10a86 | 2019-12-12 16:31:11 +0000 | [diff] [blame] | 173 | mov x1, xzr |
| 174 | mov x2, xzr |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 175 | b console_16550_core_init |
Mario Bălănică | 3bb68ae | 2023-12-01 05:12:58 +0200 | [diff] [blame^] | 176 | #endif |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 177 | endfunc plat_crash_console_init |
| 178 | |
| 179 | /* --------------------------------------------- |
| 180 | * int plat_crash_console_putc(int c) |
| 181 | * Function to print a character on the crash |
| 182 | * console without a C Runtime. |
| 183 | * Clobber list : x1, x2 |
| 184 | * --------------------------------------------- |
| 185 | */ |
| 186 | func plat_crash_console_putc |
Mario Bălănică | 3bb68ae | 2023-12-01 05:12:58 +0200 | [diff] [blame^] | 187 | mov_imm x1, PLAT_RPI_CRASH_UART_BASE |
| 188 | #if PLAT_RPI_CRASH_UART_BASE == PLAT_RPI_PL011_UART_BASE |
| 189 | b console_pl011_core_putc |
| 190 | #else |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 191 | b console_16550_core_putc |
Mario Bălănică | 3bb68ae | 2023-12-01 05:12:58 +0200 | [diff] [blame^] | 192 | #endif |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 193 | endfunc plat_crash_console_putc |
| 194 | |
| 195 | /* --------------------------------------------- |
Jimmy Brisson | 39f9eee | 2020-08-05 13:44:05 -0500 | [diff] [blame] | 196 | * void plat_crash_console_flush() |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 197 | * Function to force a write of all buffered |
| 198 | * data that hasn't been output. |
Jimmy Brisson | 39f9eee | 2020-08-05 13:44:05 -0500 | [diff] [blame] | 199 | * Out : void. |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 200 | * Clobber list : x0, x1 |
| 201 | * --------------------------------------------- |
| 202 | */ |
| 203 | func plat_crash_console_flush |
Mario Bălănică | 3bb68ae | 2023-12-01 05:12:58 +0200 | [diff] [blame^] | 204 | mov_imm x0, PLAT_RPI_CRASH_UART_BASE |
| 205 | #if PLAT_RPI_CRASH_UART_BASE == PLAT_RPI_PL011_UART_BASE |
| 206 | b console_pl011_core_flush |
| 207 | #else |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 208 | b console_16550_core_flush |
Mario Bălănică | 3bb68ae | 2023-12-01 05:12:58 +0200 | [diff] [blame^] | 209 | #endif |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 210 | endfunc plat_crash_console_flush |
| 211 | |
| 212 | /* --------------------------------------------- |
Andre Przywara | 98e4856 | 2020-03-12 14:20:04 +0000 | [diff] [blame] | 213 | * int plat_rpi_get_model() |
| 214 | * Macro to determine whether we are running on |
| 215 | * a Raspberry Pi 3 or 4. Just checks the MIDR for |
| 216 | * being either a Cortex-A72 or a Cortex-A53. |
| 217 | * Out : return 4 if RPi4, 3 otherwise. |
| 218 | * Clobber list : x0 |
| 219 | * --------------------------------------------- |
| 220 | */ |
| 221 | .macro _plat_rpi_get_model |
| 222 | mrs x0, midr_el1 |
| 223 | and x0, x0, #0xf0 /* Isolate low byte of part number */ |
| 224 | cmp w0, #0x80 /* Cortex-A72 (RPi4) is 0xd08, A53 is 0xd03 */ |
| 225 | mov w0, #3 |
| 226 | csinc w0, w0, w0, ne |
| 227 | .endm |
| 228 | |
| 229 | func plat_rpi_get_model |
| 230 | _plat_rpi_get_model |
| 231 | ret |
| 232 | endfunc plat_rpi_get_model |
| 233 | |
| 234 | /* --------------------------------------------- |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 235 | * void plat_reset_handler(void); |
| 236 | * --------------------------------------------- |
| 237 | */ |
| 238 | func plat_reset_handler |
Andre Przywara | 98e4856 | 2020-03-12 14:20:04 +0000 | [diff] [blame] | 239 | /* L2 cache setup only needed on RPi4 */ |
| 240 | _plat_rpi_get_model |
| 241 | cmp w0, #4 |
| 242 | b.ne 1f |
| 243 | |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 244 | /* ------------------------------------------------ |
| 245 | * Set L2 read/write cache latency: |
| 246 | * - L2 Data RAM latency: 3 cycles (0b010) |
| 247 | * - L2 Data RAM setup: 1 cycle (bit 5) |
| 248 | * ------------------------------------------------ |
| 249 | */ |
| 250 | mrs x0, CORTEX_A72_L2CTLR_EL1 |
| 251 | mov x1, #0x22 |
| 252 | orr x0, x0, x1 |
| 253 | msr CORTEX_A72_L2CTLR_EL1, x0 |
| 254 | isb |
| 255 | |
Andre Przywara | 98e4856 | 2020-03-12 14:20:04 +0000 | [diff] [blame] | 256 | 1: |
Andre Przywara | 6d471e1 | 2019-07-09 11:25:57 +0100 | [diff] [blame] | 257 | ret |
| 258 | endfunc plat_reset_handler |