David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __CORTEX_A75_H__ |
| 8 | #define __CORTEX_A75_H__ |
| 9 | |
| 10 | /* Cortex-A75 MIDR */ |
| 11 | #define CORTEX_A75_MIDR 0x410fd0a0 |
| 12 | |
| 13 | /******************************************************************************* |
| 14 | * CPU Extended Control register specific definitions. |
| 15 | ******************************************************************************/ |
| 16 | #define CORTEX_A75_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 17 | #define CORTEX_A75_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 18 | |
| 19 | /* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */ |
| 20 | #define CORTEX_A75_CORE_PWRDN_EN_MASK 0x1 |
| 21 | |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 22 | /******************************************************************************* |
| 23 | * CPU Activity Monitor Unit register specific definitions. |
| 24 | ******************************************************************************/ |
| 25 | #define CPUAMCNTENCLR_EL0 S3_3_C15_C9_7 |
| 26 | #define CPUAMCNTENSET_EL0 S3_3_C15_C9_6 |
| 27 | #define CPUAMCFGR_EL0 S3_3_C15_C10_6 |
| 28 | #define CPUAMUSERENR_EL0 S3_3_C15_C10_7 |
| 29 | |
| 30 | /* Activity Monitor Event Counter Registers */ |
| 31 | #define CPUAMEVCNTR0_EL0 S3_3_C15_C9_0 |
| 32 | #define CPUAMEVCNTR1_EL0 S3_3_C15_C9_1 |
| 33 | #define CPUAMEVCNTR2_EL0 S3_3_C15_C9_2 |
| 34 | #define CPUAMEVCNTR3_EL0 S3_3_C15_C9_3 |
| 35 | #define CPUAMEVCNTR4_EL0 S3_3_C15_C9_4 |
| 36 | |
| 37 | /* Activity Monitor Event Type Registers */ |
| 38 | #define CPUAMEVTYPER0_EL0 S3_3_C15_C10_0 |
| 39 | #define CPUAMEVTYPER1_EL0 S3_3_C15_C10_1 |
| 40 | #define CPUAMEVTYPER2_EL0 S3_3_C15_C10_2 |
| 41 | #define CPUAMEVTYPER3_EL0 S3_3_C15_C10_3 |
| 42 | #define CPUAMEVTYPER4_EL0 S3_3_C15_C10_4 |
| 43 | |
| 44 | #define CORTEX_A75_ACTLR_AMEN_BIT (U(1) << 4) |
| 45 | |
| 46 | /* |
| 47 | * The Cortex-A75 core implements five counters, 0-4. Events 0, 1, 2, are |
| 48 | * fixed and are enabled (Group 0). Events 3 and 4 (Group 1) are |
| 49 | * programmable by programming the appropriate Event count bits in |
| 50 | * CPUAMEVTYPER<n> register and are disabled by default. Platforms may |
| 51 | * enable this with suitable programming. |
| 52 | */ |
| 53 | #define CORTEX_A75_AMU_GROUP0_MASK 0x7 |
| 54 | #define CORTEX_A75_AMU_GROUP1_MASK (0 << 3) |
| 55 | |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 56 | #endif /* __CORTEX_A75_H__ */ |