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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch_helpers.h>
32
33 .globl read_vbar
34 .globl read_vbar_el1
35 .globl read_vbar_el2
36 .globl read_vbar_el3
37 .globl write_vbar
38 .globl write_vbar_el1
39 .globl write_vbar_el2
40 .globl write_vbar_el3
41
42 .globl read_sctlr
43 .globl read_sctlr_el1
44 .globl read_sctlr_el2
45 .globl read_sctlr_el3
46 .globl write_sctlr
47 .globl write_sctlr_el1
48 .globl write_sctlr_el2
49 .globl write_sctlr_el3
50
51 .globl read_actlr
52 .globl read_actlr_el1
53 .globl read_actlr_el2
54 .globl read_actlr_el3
55 .globl write_actlr
56 .globl write_actlr_el1
57 .globl write_actlr_el2
58 .globl write_actlr_el3
59
60 .globl read_esr
61 .globl read_esr_el1
62 .globl read_esr_el2
63 .globl read_esr_el3
64 .globl write_esr
65 .globl write_esr_el1
66 .globl write_esr_el2
67 .globl write_esr_el3
68
69 .globl read_afsr0
70 .globl read_afsr0_el1
71 .globl read_afsr0_el2
72 .globl read_afsr0_el3
73 .globl write_afsr0
74 .globl write_afsr0_el1
75 .globl write_afsr0_el2
76 .globl write_afsr0_el3
77
78 .globl read_afsr1
79 .globl read_afsr1_el1
80 .globl read_afsr1_el2
81 .globl read_afsr1_el3
82 .globl write_afsr1
83 .globl write_afsr1_el1
84 .globl write_afsr1_el2
85 .globl write_afsr1_el3
86
87 .globl read_far
88 .globl read_far_el1
89 .globl read_far_el2
90 .globl read_far_el3
91 .globl write_far
92 .globl write_far_el1
93 .globl write_far_el2
94 .globl write_far_el3
95
96 .globl read_mair
97 .globl read_mair_el1
98 .globl read_mair_el2
99 .globl read_mair_el3
100 .globl write_mair
101 .globl write_mair_el1
102 .globl write_mair_el2
103 .globl write_mair_el3
104
105 .globl read_amair
106 .globl read_amair_el1
107 .globl read_amair_el2
108 .globl read_amair_el3
109 .globl write_amair
110 .globl write_amair_el1
111 .globl write_amair_el2
112 .globl write_amair_el3
113
114 .globl read_rvbar
115 .globl read_rvbar_el1
116 .globl read_rvbar_el2
117 .globl read_rvbar_el3
118
119 .globl read_rmr
120 .globl read_rmr_el1
121 .globl read_rmr_el2
122 .globl read_rmr_el3
123 .globl write_rmr
124 .globl write_rmr_el1
125 .globl write_rmr_el2
126 .globl write_rmr_el3
127
128 .globl read_tcr
129 .globl read_tcr_el1
130 .globl read_tcr_el2
131 .globl read_tcr_el3
132 .globl write_tcr
133 .globl write_tcr_el1
134 .globl write_tcr_el2
135 .globl write_tcr_el3
136
137 .globl read_cptr
138 .globl read_cptr_el2
139 .globl read_cptr_el3
140 .globl write_cptr
141 .globl write_cptr_el2
142 .globl write_cptr_el3
143
144 .globl read_ttbr0
145 .globl read_ttbr0_el1
146 .globl read_ttbr0_el2
147 .globl read_ttbr0_el3
148 .globl write_ttbr0
149 .globl write_ttbr0_el1
150 .globl write_ttbr0_el2
151 .globl write_ttbr0_el3
152
153 .globl read_ttbr1
154 .globl read_ttbr1_el1
155 .globl read_ttbr1_el2
156 .globl write_ttbr1
157 .globl write_ttbr1_el1
158 .globl write_ttbr1_el2
159
160 .globl read_cpacr
161 .globl write_cpacr
162
163 .globl read_cntfrq
164 .globl write_cntfrq
165
166 .globl read_cpuectlr
167 .globl write_cpuectlr
168
169 .globl read_cnthctl_el2
170 .globl write_cnthctl_el2
171
172 .globl read_cntfrq_el0
173 .globl write_cntfrq_el0
174
175 .globl read_scr
176 .globl write_scr
177
178 .globl read_hcr
179 .globl write_hcr
180
181 .globl read_midr
182 .globl read_mpidr
183
184 .globl read_current_el
185 .globl read_id_pfr1_el1
186 .globl read_id_aa64pfr0_el1
187
188#if SUPPORT_VFP
189 .globl enable_vfp
190 .globl read_fpexc
191 .globl write_fpexc
192#endif
193
194
195 .section .text, "ax"
196
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000197read_current_el: ; .type read_current_el, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100198 mrs x0, CurrentEl
199 ret
200
201
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000202read_id_pfr1_el1: ; .type read_id_pfr1_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100203 mrs x0, id_pfr1_el1
204 ret
205
206
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000207read_id_aa64pfr0_el1: ; .type read_id_aa64pfr0_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100208 mrs x0, id_aa64pfr0_el1
209 ret
210
211
212 /* -----------------------------------------------------
213 * VBAR accessors
214 * -----------------------------------------------------
215 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000216read_vbar: ; .type read_vbar, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100217 mrs x0, CurrentEl
218 cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
219 b.eq read_vbar_el1
220 cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
221 b.eq read_vbar_el2
222 cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
223 b.eq read_vbar_el3
224
225
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000226read_vbar_el1: ; .type read_vbar_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100227 mrs x0, vbar_el1
228 ret
229
230
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000231read_vbar_el2: ; .type read_vbar_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100232 mrs x0, vbar_el2
233 ret
234
235
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000236read_vbar_el3: ; .type read_vbar_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100237 mrs x0, vbar_el3
238 ret
239
240
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000241write_vbar: ; .type write_vbar, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100242 mrs x1, CurrentEl
243 cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
244 b.eq write_vbar_el1
245 cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
246 b.eq write_vbar_el2
247 cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
248 b.eq write_vbar_el3
249
250
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000251write_vbar_el1: ; .type write_vbar_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100252 msr vbar_el1, x0
253 isb
254 ret
255
256
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000257write_vbar_el2: ; .type write_vbar_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100258 msr vbar_el2, x0
259 isb
260 ret
261
262
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000263write_vbar_el3: ; .type write_vbar_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100264 msr vbar_el3, x0
265 isb
266 ret
267
268
269 /* -----------------------------------------------------
270 * AFSR0 accessors
271 * -----------------------------------------------------
272 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000273read_afsr0: ; .type read_afsr0, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100274 mrs x0, CurrentEl
275 cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
276 b.eq read_afsr0_el1
277 cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
278 b.eq read_afsr0_el2
279 cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
280 b.eq read_afsr0_el3
281
282
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000283read_afsr0_el1: ; .type read_afsr0_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100284 mrs x0, afsr0_el1
285 ret
286
287
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000288read_afsr0_el2: ; .type read_afsr0_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100289 mrs x0, afsr0_el2
290 ret
291
292
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000293read_afsr0_el3: ; .type read_afsr0_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100294 mrs x0, afsr0_el3
295 ret
296
297
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000298write_afsr0: ; .type write_afsr0, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100299 mrs x1, CurrentEl
300 cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
301 b.eq write_afsr0_el1
302 cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
303 b.eq write_afsr0_el2
304 cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
305 b.eq write_afsr0_el3
306
307
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000308write_afsr0_el1: ; .type write_afsr0_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100309 msr afsr0_el1, x0
310 isb
311 ret
312
313
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000314write_afsr0_el2: ; .type write_afsr0_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100315 msr afsr0_el2, x0
316 isb
317 ret
318
319
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000320write_afsr0_el3: ; .type write_afsr0_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100321 msr afsr0_el3, x0
322 isb
323 ret
324
325
326 /* -----------------------------------------------------
327 * FAR accessors
328 * -----------------------------------------------------
329 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000330read_far: ; .type read_far, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100331 mrs x0, CurrentEl
332 cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
333 b.eq read_far_el1
334 cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
335 b.eq read_far_el2
336 cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
337 b.eq read_far_el3
338
339
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000340read_far_el1: ; .type read_far_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100341 mrs x0, far_el1
342 ret
343
344
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000345read_far_el2: ; .type read_far_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100346 mrs x0, far_el2
347 ret
348
349
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000350read_far_el3: ; .type read_far_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100351 mrs x0, far_el3
352 ret
353
354
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000355write_far: ; .type write_far, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100356 mrs x1, CurrentEl
357 cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
358 b.eq write_far_el1
359 cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
360 b.eq write_far_el2
361 cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
362 b.eq write_far_el3
363
364
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000365write_far_el1: ; .type write_far_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100366 msr far_el1, x0
367 isb
368 ret
369
370
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000371write_far_el2: ; .type write_far_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100372 msr far_el2, x0
373 isb
374 ret
375
376
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000377write_far_el3: ; .type write_far_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100378 msr far_el3, x0
379 isb
380 ret
381
382
383 /* -----------------------------------------------------
384 * MAIR accessors
385 * -----------------------------------------------------
386 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000387read_mair: ; .type read_mair, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100388 mrs x0, CurrentEl
389 cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
390 b.eq read_mair_el1
391 cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
392 b.eq read_mair_el2
393 cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
394 b.eq read_mair_el3
395
396
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000397read_mair_el1: ; .type read_mair_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100398 mrs x0, mair_el1
399 ret
400
401
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000402read_mair_el2: ; .type read_mair_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100403 mrs x0, mair_el2
404 ret
405
406
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000407read_mair_el3: ; .type read_mair_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100408 mrs x0, mair_el3
409 ret
410
411
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000412write_mair: ; .type write_mair, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100413 mrs x1, CurrentEl
414 cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
415 b.eq write_mair_el1
416 cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
417 b.eq write_mair_el2
418 cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
419 b.eq write_mair_el3
420
421
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000422write_mair_el1: ; .type write_mair_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100423 msr mair_el1, x0
424 isb
425 ret
426
427
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000428write_mair_el2: ; .type write_mair_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100429 msr mair_el2, x0
430 isb
431 ret
432
433
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000434write_mair_el3: ; .type write_mair_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100435 msr mair_el3, x0
436 isb
437 ret
438
439
440 /* -----------------------------------------------------
441 * AMAIR accessors
442 * -----------------------------------------------------
443 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000444read_amair: ; .type read_amair, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100445 mrs x0, CurrentEl
446 cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
447 b.eq read_amair_el1
448 cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
449 b.eq read_amair_el2
450 cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
451 b.eq read_amair_el3
452
453
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000454read_amair_el1: ; .type read_amair_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100455 mrs x0, amair_el1
456 ret
457
458
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000459read_amair_el2: ; .type read_amair_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100460 mrs x0, amair_el2
461 ret
462
463
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000464read_amair_el3: ; .type read_amair_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100465 mrs x0, amair_el3
466 ret
467
468
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000469write_amair: ; .type write_amair, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100470 mrs x1, CurrentEl
471 cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
472 b.eq write_amair_el1
473 cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
474 b.eq write_amair_el2
475 cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
476 b.eq write_amair_el3
477
478
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000479write_amair_el1: ; .type write_amair_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100480 msr amair_el1, x0
481 isb
482 ret
483
484
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000485write_amair_el2: ; .type write_amair_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100486 msr amair_el2, x0
487 isb
488 ret
489
490
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000491write_amair_el3: ; .type write_amair_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100492 msr amair_el3, x0
493 isb
494 ret
495
496
497 /* -----------------------------------------------------
498 * RVBAR accessors
499 * -----------------------------------------------------
500 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000501read_rvbar: ; .type read_rvbar, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100502 mrs x0, CurrentEl
503 cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
504 b.eq read_rvbar_el1
505 cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
506 b.eq read_rvbar_el2
507 cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
508 b.eq read_rvbar_el3
509
510
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000511read_rvbar_el1: ; .type read_rvbar_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100512 mrs x0, rvbar_el1
513 ret
514
515
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000516read_rvbar_el2: ; .type read_rvbar_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100517 mrs x0, rvbar_el2
518 ret
519
520
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000521read_rvbar_el3: ; .type read_rvbar_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100522 mrs x0, rvbar_el3
523 ret
524
525
526 /* -----------------------------------------------------
527 * RMR accessors
528 * -----------------------------------------------------
529 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000530read_rmr: ; .type read_rmr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100531 mrs x0, CurrentEl
532 cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
533 b.eq read_rmr_el1
534 cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
535 b.eq read_rmr_el2
536 cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
537 b.eq read_rmr_el3
538
539
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000540read_rmr_el1: ; .type read_rmr_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100541 mrs x0, rmr_el1
542 ret
543
544
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000545read_rmr_el2: ; .type read_rmr_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100546 mrs x0, rmr_el2
547 ret
548
549
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000550read_rmr_el3: ; .type read_rmr_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100551 mrs x0, rmr_el3
552 ret
553
554
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000555write_rmr: ; .type write_rmr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100556 mrs x1, CurrentEl
557 cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
558 b.eq write_rmr_el1
559 cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
560 b.eq write_rmr_el2
561 cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
562 b.eq write_rmr_el3
563
564
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000565write_rmr_el1: ; .type write_rmr_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100566 msr rmr_el1, x0
567 isb
568 ret
569
570
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000571write_rmr_el2: ; .type write_rmr_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100572 msr rmr_el2, x0
573 isb
574 ret
575
576
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000577write_rmr_el3: ; .type write_rmr_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100578 msr rmr_el3, x0
579 isb
580 ret
581
582
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000583read_afsr1: ; .type read_afsr1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100584 mrs x0, CurrentEl
585 cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
586 b.eq read_afsr1_el1
587 cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
588 b.eq read_afsr1_el2
589 cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
590 b.eq read_afsr1_el3
591
592
593 /* -----------------------------------------------------
594 * AFSR1 accessors
595 * -----------------------------------------------------
596 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000597read_afsr1_el1: ; .type read_afsr1_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100598 mrs x0, afsr1_el1
599 ret
600
601
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000602read_afsr1_el2: ; .type read_afsr1_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100603 mrs x0, afsr1_el2
604 ret
605
606
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000607read_afsr1_el3: ; .type read_afsr1_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100608 mrs x0, afsr1_el3
609 ret
610
611
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000612write_afsr1: ; .type write_afsr1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100613 mrs x1, CurrentEl
614 cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
615 b.eq write_afsr1_el1
616 cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
617 b.eq write_afsr1_el2
618 cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
619 b.eq write_afsr1_el3
620
621
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000622write_afsr1_el1: ; .type write_afsr1_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100623 msr afsr1_el1, x0
624 isb
625 ret
626
627
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000628write_afsr1_el2: ; .type write_afsr1_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100629 msr afsr1_el2, x0
630 isb
631 ret
632
633
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000634write_afsr1_el3: ; .type write_afsr1_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100635 msr afsr1_el3, x0
636 isb
637 ret
638
639
640 /* -----------------------------------------------------
641 * SCTLR accessors
642 * -----------------------------------------------------
643 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000644read_sctlr: ; .type read_sctlr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100645 mrs x0, CurrentEl
646 cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
647 b.eq read_sctlr_el1
648 cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
649 b.eq read_sctlr_el2
650 cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
651 b.eq read_sctlr_el3
652
653
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000654read_sctlr_el1: ; .type read_sctlr_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100655 mrs x0, sctlr_el1
656 ret
657
658
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000659read_sctlr_el2: ; .type read_sctlr_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100660 mrs x0, sctlr_el2
661 ret
662
663
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000664read_sctlr_el3: ; .type read_sctlr_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100665 mrs x0, sctlr_el3
666 ret
667
668
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000669write_sctlr: ; .type write_sctlr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100670 mrs x1, CurrentEl
671 cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
672 b.eq write_sctlr_el1
673 cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
674 b.eq write_sctlr_el2
675 cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
676 b.eq write_sctlr_el3
677
678
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000679write_sctlr_el1: ; .type write_sctlr_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100680 msr sctlr_el1, x0
681 dsb sy
682 isb
683 ret
684
685
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000686write_sctlr_el2: ; .type write_sctlr_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100687 msr sctlr_el2, x0
688 dsb sy
689 isb
690 ret
691
692
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000693write_sctlr_el3: ; .type write_sctlr_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100694 msr sctlr_el3, x0
695 dsb sy
696 isb
697 ret
698
699
700 /* -----------------------------------------------------
701 * ACTLR accessors
702 * -----------------------------------------------------
703 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000704read_actlr: ; .type read_actlr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100705 mrs x0, CurrentEl
706 cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
707 b.eq read_actlr_el1
708 cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
709 b.eq read_actlr_el2
710 cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
711 b.eq read_actlr_el3
712
713
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000714read_actlr_el1: ; .type read_actlr_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100715 mrs x0, actlr_el1
716 ret
717
718
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000719read_actlr_el2: ; .type read_actlr_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100720 mrs x0, actlr_el2
721 ret
722
723
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000724read_actlr_el3: ; .type read_actlr_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100725 mrs x0, actlr_el3
726 ret
727
728
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000729write_actlr: ; .type write_actlr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100730 mrs x1, CurrentEl
731 cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
732 b.eq write_actlr_el1
733 cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
734 b.eq write_actlr_el2
735 cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
736 b.eq write_actlr_el3
737
738
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000739write_actlr_el1: ; .type write_actlr_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100740 msr actlr_el1, x0
741 dsb sy
742 isb
743 ret
744
745
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000746write_actlr_el2: ; .type write_actlr_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100747 msr actlr_el2, x0
748 dsb sy
749 isb
750 ret
751
752
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000753write_actlr_el3: ; .type write_actlr_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100754 msr actlr_el3, x0
755 dsb sy
756 isb
757 ret
758
759
760 /* -----------------------------------------------------
761 * ESR accessors
762 * -----------------------------------------------------
763 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000764read_esr: ; .type read_esr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100765 mrs x0, CurrentEl
766 cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
767 b.eq read_esr_el1
768 cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
769 b.eq read_esr_el2
770 cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
771 b.eq read_esr_el3
772
773
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000774read_esr_el1: ; .type read_esr_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100775 mrs x0, esr_el1
776 ret
777
778
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000779read_esr_el2: ; .type read_esr_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100780 mrs x0, esr_el2
781 ret
782
783
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000784read_esr_el3: ; .type read_esr_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100785 mrs x0, esr_el3
786 ret
787
788
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000789write_esr: ; .type write_esr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100790 mrs x1, CurrentEl
791 cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
792 b.eq write_esr_el1
793 cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
794 b.eq write_esr_el2
795 cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
796 b.eq write_esr_el3
797
798
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000799write_esr_el1: ; .type write_esr_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100800 msr esr_el1, x0
801 dsb sy
802 isb
803 ret
804
805
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000806write_esr_el2: ; .type write_esr_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100807 msr esr_el2, x0
808 dsb sy
809 isb
810 ret
811
812
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000813write_esr_el3: ; .type write_esr_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100814 msr esr_el3, x0
815 dsb sy
816 isb
817 ret
818
819
820 /* -----------------------------------------------------
821 * TCR accessors
822 * -----------------------------------------------------
823 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000824read_tcr: ; .type read_tcr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100825 mrs x0, CurrentEl
826 cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
827 b.eq read_tcr_el1
828 cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
829 b.eq read_tcr_el2
830 cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
831 b.eq read_tcr_el3
832
833
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000834read_tcr_el1: ; .type read_tcr_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100835 mrs x0, tcr_el1
836 ret
837
838
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000839read_tcr_el2: ; .type read_tcr_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100840 mrs x0, tcr_el2
841 ret
842
843
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000844read_tcr_el3: ; .type read_tcr_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100845 mrs x0, tcr_el3
846 ret
847
848
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000849write_tcr: ; .type write_tcr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100850 mrs x1, CurrentEl
851 cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
852 b.eq write_tcr_el1
853 cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
854 b.eq write_tcr_el2
855 cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
856 b.eq write_tcr_el3
857
858
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000859write_tcr_el1: ; .type write_tcr_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100860 msr tcr_el1, x0
861 dsb sy
862 isb
863 ret
864
865
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000866write_tcr_el2: ; .type write_tcr_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100867 msr tcr_el2, x0
868 dsb sy
869 isb
870 ret
871
872
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000873write_tcr_el3: ; .type write_tcr_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100874 msr tcr_el3, x0
875 dsb sy
876 isb
877 ret
878
879
880 /* -----------------------------------------------------
881 * CPTR accessors
882 * -----------------------------------------------------
883 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000884read_cptr: ; .type read_cptr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100885 mrs x0, CurrentEl
886 cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
887 b.eq read_cptr_el1
888 cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
889 b.eq read_cptr_el2
890 cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
891 b.eq read_cptr_el3
892
893
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000894read_cptr_el1: ; .type read_cptr_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100895 b read_cptr_el1
896 ret
897
898
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000899read_cptr_el2: ; .type read_cptr_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100900 mrs x0, cptr_el2
901 ret
902
903
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000904read_cptr_el3: ; .type read_cptr_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100905 mrs x0, cptr_el3
906 ret
907
908
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000909write_cptr: ; .type write_cptr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100910 mrs x1, CurrentEl
911 cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
912 b.eq write_cptr_el1
913 cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
914 b.eq write_cptr_el2
915 cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
916 b.eq write_cptr_el3
917
918
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000919write_cptr_el1: ; .type write_cptr_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100920 b write_cptr_el1
921
922
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000923write_cptr_el2: ; .type write_cptr_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100924 msr cptr_el2, x0
925 dsb sy
926 isb
927 ret
928
929
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000930write_cptr_el3: ; .type write_cptr_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100931 msr cptr_el3, x0
932 dsb sy
933 isb
934 ret
935
936
937 /* -----------------------------------------------------
938 * TTBR0 accessors
939 * -----------------------------------------------------
940 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000941read_ttbr0: ; .type read_ttbr0, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100942 mrs x0, CurrentEl
943 cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
944 b.eq read_ttbr0_el1
945 cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
946 b.eq read_ttbr0_el2
947 cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
948 b.eq read_ttbr0_el3
949
950
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000951read_ttbr0_el1: ; .type read_ttbr0_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100952 mrs x0, ttbr0_el1
953 ret
954
955
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000956read_ttbr0_el2: ; .type read_ttbr0_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100957 mrs x0, ttbr0_el2
958 ret
959
960
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000961read_ttbr0_el3: ; .type read_ttbr0_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100962 mrs x0, ttbr0_el3
963 ret
964
965
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000966write_ttbr0: ; .type write_ttbr0, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100967 mrs x1, CurrentEl
968 cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
969 b.eq write_ttbr0_el1
970 cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
971 b.eq write_ttbr0_el2
972 cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
973 b.eq write_ttbr0_el3
974
975
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000976write_ttbr0_el1: ; .type write_ttbr0_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100977 msr ttbr0_el1, x0
978 isb
979 ret
980
981
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000982write_ttbr0_el2: ; .type write_ttbr0_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100983 msr ttbr0_el2, x0
984 isb
985 ret
986
987
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000988write_ttbr0_el3: ; .type write_ttbr0_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100989 msr ttbr0_el3, x0
990 isb
991 ret
992
993
994 /* -----------------------------------------------------
995 * TTBR1 accessors
996 * -----------------------------------------------------
997 */
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000998read_ttbr1: ; .type read_ttbr1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100999 mrs x0, CurrentEl
1000 cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
1001 b.eq read_ttbr1_el1
1002 cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
1003 b.eq read_ttbr1_el2
1004 cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
1005 b.eq read_ttbr1_el3
1006
1007
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001008read_ttbr1_el1: ; .type read_ttbr1_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001009 mrs x0, ttbr1_el1
1010 ret
1011
1012
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001013read_ttbr1_el2: ; .type read_ttbr1_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001014 b read_ttbr1_el2
1015
1016
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001017read_ttbr1_el3: ; .type read_ttbr1_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001018 b read_ttbr1_el3
1019
1020
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001021write_ttbr1: ; .type write_ttbr1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001022 mrs x1, CurrentEl
1023 cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
1024 b.eq write_ttbr1_el1
1025 cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
1026 b.eq write_ttbr1_el2
1027 cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
1028 b.eq write_ttbr1_el3
1029
1030
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001031write_ttbr1_el1: ; .type write_ttbr1_el1, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001032 msr ttbr1_el1, x0
1033 isb
1034 ret
1035
1036
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001037write_ttbr1_el2: ; .type write_ttbr1_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001038 b write_ttbr1_el2
1039
1040
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001041write_ttbr1_el3: ; .type write_ttbr1_el3, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001042 b write_ttbr1_el3
1043
1044
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001045read_hcr: ; .type read_hcr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001046 mrs x0, hcr_el2
1047 ret
1048
1049
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001050write_hcr: ; .type write_hcr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001051 msr hcr_el2, x0
1052 dsb sy
1053 isb
1054 ret
1055
1056
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001057read_cpacr: ; .type read_cpacr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001058 mrs x0, cpacr_el1
1059 ret
1060
1061
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001062write_cpacr: ; .type write_cpacr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001063 msr cpacr_el1, x0
1064 ret
1065
1066
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001067read_cntfrq_el0: ; .type read_cntfrq_el0, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001068 mrs x0, cntfrq_el0
1069 ret
1070
1071
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001072write_cntfrq_el0: ; .type write_cntfrq_el0, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001073 msr cntfrq_el0, x0
1074 ret
1075
1076
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001077read_cpuectlr: ; .type read_cpuectlr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001078 mrs x0, CPUECTLR_EL1
1079 ret
1080
1081
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001082write_cpuectlr: ; .type write_cpuectlr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001083 msr CPUECTLR_EL1, x0
1084 dsb sy
1085 isb
1086 ret
1087
1088
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001089read_cnthctl_el2: ; .type read_cnthctl_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001090 mrs x0, cnthctl_el2
1091 ret
1092
1093
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001094write_cnthctl_el2: ; .type write_cnthctl_el2, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001095 msr cnthctl_el2, x0
1096 ret
1097
1098
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001099read_cntfrq: ; .type read_cntfrq, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001100 mrs x0, cntfrq_el0
1101 ret
1102
1103
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001104write_cntfrq: ; .type write_cntfrq, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001105 msr cntfrq_el0, x0
1106 ret
1107
1108
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001109write_scr: ; .type write_scr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001110 msr scr_el3, x0
1111 dsb sy
1112 isb
1113 ret
1114
1115
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001116read_scr: ; .type read_scr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001117 mrs x0, scr_el3
1118 ret
1119
1120
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001121read_midr: ; .type read_midr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001122 mrs x0, midr_el1
1123 ret
1124
1125
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001126read_mpidr: ; .type read_mpidr, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001127 mrs x0, mpidr_el1
1128 ret
1129
1130
1131#if SUPPORT_VFP
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001132enable_vfp: ; .type enable_vfp, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001133 mrs x0, cpacr_el1
1134 orr x0, x0, #CPACR_VFP_BITS
1135 msr cpacr_el1, x0
1136 mrs x0, cptr_el3
1137 mov x1, #AARCH64_CPTR_TFP
1138 bic x0, x0, x1
1139 msr cptr_el3, x0
1140 ret
1141
1142
1143 // int read_fpexc(void)
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001144read_fpexc: ; .type read_fpexc, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001145 b read_fpexc
1146 ret
1147
1148
1149 // void write_fpexc(int fpexc)
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +00001150write_fpexc: ; .type write_fpexc, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +01001151 b write_fpexc
1152 ret
1153
1154#endif