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git01.mediatek.com / filogic / atf / 3a4cae051af8fb129054c0aaf14dd3b7247f04f0 / . / bl2 / aarch64 / bl2_entrypoint.S
blob: ebb3b94bfdde1a3ebff8af715064fcd6e57877be [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]1/*
Dan Handleye83b0ca2014-01-14 18:17:09 +0000[diff] [blame]2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <bl_common.h>
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +0000[diff] [blame]32#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]33
34
35 .globl bl2_entrypoint
36
37
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000[diff] [blame]38 .section .text, "ax"; .align 3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]39
40
Jeenu Viswambharan3a4cae02014-01-16 17:30:39 +0000[diff] [blame^]41bl2_entrypoint: ; .type bl2_entrypoint, %function
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]42 /*---------------------------------------------
43 * Store the extents of the tzram available to
44 * BL2 for future use. Use the opcode param to
45 * allow implement other functions if needed.
46 * ---------------------------------------------
47 */
48 mov x20, x0
49 mov x21, x1
50 mov x22, x2
51
52 /* ---------------------------------------------
53 * This is BL2 which is expected to be executed
54 * only by the primary cpu (at least for now).
55 * So, make sure no secondary has lost its way.
56 * ---------------------------------------------
57 */
58 bl read_mpidr
59 mov x19, x0
60 bl platform_is_primary_cpu
61 cbz x0, _panic
62
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +0000[diff] [blame]63 /* ---------------------------------------------
64 * Set the exception vector to something sane.
65 * ---------------------------------------------
66 */
67 adr x0, early_exceptions
68 msr vbar_el1, x0
69
70 /* ---------------------------------------------
71 * Enable the instruction cache.
72 * ---------------------------------------------
73 */
74 mrs x0, sctlr_el1
75 orr x0, x0, #SCTLR_I_BIT
76 msr sctlr_el1, x0
77
78 isb
79
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000[diff] [blame]80 /* ---------------------------------------------
Sandrine Bailleux34edaed2013-12-02 15:45:07 +0000[diff] [blame]81 * Check the opcodes out of paranoia.
82 * ---------------------------------------------
83 */
84 mov x0, #RUN_IMAGE
85 cmp x0, x20
86 b.ne _panic
87
88 /* ---------------------------------------------
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000[diff] [blame]89 * Zero out NOBITS sections. There are 2 of them:
90 * - the .bss section;
91 * - the coherent memory section.
92 * ---------------------------------------------
93 */
94 ldr x0, =__BSS_START__
95 ldr x1, =__BSS_SIZE__
96 bl zeromem16
97
98 ldr x0, =__COHERENT_RAM_START__
99 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
100 bl zeromem16
101
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]102 /* --------------------------------------------
103 * Give ourselves a small coherent stack to
104 * ease the pain of initializing the MMU
105 * --------------------------------------------
106 */
107 mov x0, x19
108 bl platform_set_coherent_stack
109
110 /* ---------------------------------------------
111 * Perform early platform setup & platform
112 * specific early arch. setup e.g. mmu setup
113 * ---------------------------------------------
114 */
115 mov x0, x21
116 mov x1, x22
117 bl bl2_early_platform_setup
118 bl bl2_plat_arch_setup
119
120 /* ---------------------------------------------
121 * Give ourselves a stack allocated in Normal
122 * -IS-WBWA memory
123 * ---------------------------------------------
124 */
125 mov x0, x19
126 bl platform_set_stack
127
128 /* ---------------------------------------------
129 * Jump to main function.
130 * ---------------------------------------------
131 */
132 bl bl2_main
133_panic:
134 b _panic