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Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00001/*
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05002 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <assert_macros.S>
10#include <platform_def.h>
11
12 .globl plat_crash_console_flush
13 .globl plat_crash_console_init
14 .globl plat_crash_console_putc
15 .globl platform_mem_init
16 .globl plat_is_my_cpu_primary
17 .globl plat_my_core_pos
18 .globl plat_reset_handler
Carlo Caione1afdfb02019-08-24 18:47:06 +010019 .globl plat_calc_core_pos
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000020
21 /* -----------------------------------------------------
22 * unsigned int plat_my_core_pos(void);
23 * -----------------------------------------------------
24 */
25func plat_my_core_pos
26 mrs x0, mpidr_el1
Carlo Caione1afdfb02019-08-24 18:47:06 +010027 b plat_calc_core_pos
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000028endfunc plat_my_core_pos
29
30 /* -----------------------------------------------------
Carlo Caione1afdfb02019-08-24 18:47:06 +010031 * unsigned int plat_calc_core_pos(u_register_t mpidr);
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000032 * -----------------------------------------------------
33 */
Carlo Caione1afdfb02019-08-24 18:47:06 +010034func plat_calc_core_pos
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000035 and x0, x0, #MPIDR_CPU_MASK
36 ret
Carlo Caione1afdfb02019-08-24 18:47:06 +010037endfunc plat_calc_core_pos
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000038
39 /* -----------------------------------------------------
40 * unsigned int plat_is_my_cpu_primary(void);
41 * -----------------------------------------------------
42 */
43func plat_is_my_cpu_primary
44 mrs x0, mpidr_el1
45 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
Carlo Caione1afdfb02019-08-24 18:47:06 +010046 cmp x0, #AML_PRIMARY_CPU
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000047 cset w0, eq
48 ret
49endfunc plat_is_my_cpu_primary
50
51 /* ---------------------------------------------
52 * void platform_mem_init(void);
53 * ---------------------------------------------
54 */
55func platform_mem_init
56 ret
57endfunc platform_mem_init
58
59 /* ---------------------------------------------
60 * int plat_crash_console_init(void)
61 * ---------------------------------------------
62 */
63func plat_crash_console_init
Carlo Caione1afdfb02019-08-24 18:47:06 +010064 mov_imm x0, AML_UART0_AO_BASE
65 mov_imm x1, AML_UART0_AO_CLK_IN_HZ
66 mov_imm x2, AML_UART_BAUDRATE
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000067 b console_meson_init
68endfunc plat_crash_console_init
69
70 /* ---------------------------------------------
71 * int plat_crash_console_putc(int c)
72 * Clobber list : x1, x2
73 * ---------------------------------------------
74 */
75func plat_crash_console_putc
Carlo Caione1afdfb02019-08-24 18:47:06 +010076 mov_imm x1, AML_UART0_AO_BASE
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000077 b console_meson_core_putc
78endfunc plat_crash_console_putc
79
80 /* ---------------------------------------------
Jimmy Brisson39f9eee2020-08-05 13:44:05 -050081 * void plat_crash_console_flush()
82 * Out : void.
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000083 * Clobber list : x0, x1
84 * ---------------------------------------------
85 */
86func plat_crash_console_flush
Carlo Caione1afdfb02019-08-24 18:47:06 +010087 mov_imm x0, AML_UART0_AO_BASE
Antonio Nino Diaz7298c1f2018-12-05 00:09:30 +000088 b console_meson_core_flush
89endfunc plat_crash_console_flush
90
91 /* ---------------------------------------------
92 * void plat_reset_handler(void);
93 * ---------------------------------------------
94 */
95func plat_reset_handler
96 ret
97endfunc plat_reset_handler