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git01.mediatek.com / filogic / atf / 39f9eeef9b606a44cf334e0d22bf59b1a149b1c4 / . / fdts / stm32mp151.dtsi
blob: 2eb4a3943932729b40679f55694902c4e70e02ef [file] [log] [blame]
Yann Gautier4ede20a2020-09-18 15:04:14 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 device_type = "cpu";
21 reg = <0>;
22 };
23 };
24
25 psci {
26 compatible = "arm,psci-1.0";
27 method = "smc";
28 };
29
30 intc: interrupt-controller@a0021000 {
31 compatible = "arm,cortex-a7-gic";
32 #interrupt-cells = <3>;
33 interrupt-controller;
34 reg = <0xa0021000 0x1000>,
35 <0xa0022000 0x2000>;
36 };
37
38 clocks {
39 clk_hse: clk-hse {
40 #clock-cells = <0>;
41 compatible = "fixed-clock";
42 clock-frequency = <24000000>;
43 };
44
45 clk_hsi: clk-hsi {
46 #clock-cells = <0>;
47 compatible = "fixed-clock";
48 clock-frequency = <64000000>;
49 };
50
51 clk_lse: clk-lse {
52 #clock-cells = <0>;
53 compatible = "fixed-clock";
54 clock-frequency = <32768>;
55 };
56
57 clk_lsi: clk-lsi {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <32000>;
61 };
62
63 clk_csi: clk-csi {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <4000000>;
67 };
68 };
69
70 soc {
71 compatible = "simple-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 interrupt-parent = <&intc>;
75 ranges;
76
77 timers12: timer@40006000 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 compatible = "st,stm32-timers";
81 reg = <0x40006000 0x400>;
82 clocks = <&rcc TIM12_K>;
83 clock-names = "int";
84 status = "disabled";
85 };
86
87 usart2: serial@4000e000 {
88 compatible = "st,stm32h7-uart";
89 reg = <0x4000e000 0x400>;
90 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
91 clocks = <&rcc USART2_K>;
92 resets = <&rcc USART2_R>;
93 status = "disabled";
94 };
95
96 usart3: serial@4000f000 {
97 compatible = "st,stm32h7-uart";
98 reg = <0x4000f000 0x400>;
99 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&rcc USART3_K>;
101 resets = <&rcc USART3_R>;
102 status = "disabled";
103 };
104
105 uart4: serial@40010000 {
106 compatible = "st,stm32h7-uart";
107 reg = <0x40010000 0x400>;
108 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
109 clocks = <&rcc UART4_K>;
110 resets = <&rcc UART4_R>;
111 wakeup-source;
112 status = "disabled";
113 };
114
115 uart5: serial@40011000 {
116 compatible = "st,stm32h7-uart";
117 reg = <0x40011000 0x400>;
118 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&rcc UART5_K>;
120 resets = <&rcc UART5_R>;
121 status = "disabled";
122 };
123
124 uart7: serial@40018000 {
125 compatible = "st,stm32h7-uart";
126 reg = <0x40018000 0x400>;
127 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&rcc UART7_K>;
129 resets = <&rcc UART7_R>;
130 status = "disabled";
131 };
132
133 uart8: serial@40019000 {
134 compatible = "st,stm32h7-uart";
135 reg = <0x40019000 0x400>;
136 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&rcc UART8_K>;
138 resets = <&rcc UART8_R>;
139 status = "disabled";
140 };
141
142 usart6: serial@44003000 {
143 compatible = "st,stm32h7-uart";
144 reg = <0x44003000 0x400>;
145 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&rcc USART6_K>;
147 resets = <&rcc USART6_R>;
148 status = "disabled";
149 };
150
151 timers15: timer@44006000 {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 compatible = "st,stm32-timers";
155 reg = <0x44006000 0x400>;
156 clocks = <&rcc TIM15_K>;
157 clock-names = "int";
158 status = "disabled";
159 };
160
161 usbotg_hs: usb-otg@49000000 {
162 compatible = "st,stm32mp1-hsotg", "snps,dwc2";
163 reg = <0x49000000 0x10000>;
164 clocks = <&rcc USBO_K>;
165 clock-names = "otg";
166 resets = <&rcc USBO_R>;
167 reset-names = "dwc2";
168 interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
169 g-rx-fifo-size = <512>;
170 g-np-tx-fifo-size = <32>;
171 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
172 dr_mode = "otg";
173 usb33d-supply = <&usb33>;
174 status = "disabled";
175 };
176
177 rcc: rcc@50000000 {
178 compatible = "st,stm32mp1-rcc", "syscon";
179 reg = <0x50000000 0x1000>;
180 #address-cells = <1>;
181 #size-cells = <0>;
182 #clock-cells = <1>;
183 #reset-cells = <1>;
184 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
185 secure-interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
186 secure-interrupt-names = "wakeup";
187 };
188
189 pwr_regulators: pwr@50001000 {
190 compatible = "st,stm32mp1,pwr-reg";
191 reg = <0x50001000 0x10>;
192 st,tzcr = <&rcc 0x0 0x1>;
193
194 reg11: reg11 {
195 regulator-name = "reg11";
196 regulator-min-microvolt = <1100000>;
197 regulator-max-microvolt = <1100000>;
198 };
199
200 reg18: reg18 {
201 regulator-name = "reg18";
202 regulator-min-microvolt = <1800000>;
203 regulator-max-microvolt = <1800000>;
204 };
205
206 usb33: usb33 {
207 regulator-name = "usb33";
208 regulator-min-microvolt = <3300000>;
209 regulator-max-microvolt = <3300000>;
210 };
211 };
212
213 pwr_mcu: pwr_mcu@50001014 {
214 compatible = "st,stm32mp151-pwr-mcu", "syscon";
215 reg = <0x50001014 0x4>;
216 };
217
218 pwr_irq: pwr@50001020 {
219 compatible = "st,stm32mp1-pwr";
220 reg = <0x50001020 0x100>;
221 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
222 interrupt-controller;
223 #interrupt-cells = <3>;
224 };
225
226 exti: interrupt-controller@5000d000 {
227 compatible = "st,stm32mp1-exti", "syscon";
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 reg = <0x5000d000 0x400>;
231
232 /* exti_pwr is an extra interrupt controller used for
233 * EXTI 55 to 60. It's mapped on pwr interrupt
234 * controller.
235 */
236 exti_pwr: exti-pwr {
237 interrupt-controller;
238 #interrupt-cells = <2>;
239 interrupt-parent = <&pwr_irq>;
240 st,irq-number = <6>;
241 };
242 };
243
244 syscfg: syscon@50020000 {
245 compatible = "st,stm32mp157-syscfg", "syscon";
246 reg = <0x50020000 0x400>;
247 clocks = <&rcc SYSCFG>;
248 };
249
250 hash1: hash@54002000 {
251 compatible = "st,stm32f756-hash";
252 reg = <0x54002000 0x400>;
253 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&rcc HASH1>;
255 resets = <&rcc HASH1_R>;
256 status = "disabled";
257 };
258
259 rng1: rng@54003000 {
260 compatible = "st,stm32-rng";
261 reg = <0x54003000 0x400>;
262 clocks = <&rcc RNG1_K>;
263 resets = <&rcc RNG1_R>;
264 status = "disabled";
265 };
266
267 fmc: nand-controller@58002000 {
268 compatible = "st,stm32mp15-fmc2";
269 reg = <0x58002000 0x1000>,
270 <0x80000000 0x1000>,
271 <0x88010000 0x1000>,
272 <0x88020000 0x1000>,
273 <0x81000000 0x1000>,
274 <0x89010000 0x1000>,
275 <0x89020000 0x1000>;
276 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&rcc FMC_K>;
278 resets = <&rcc FMC_R>;
279 status = "disabled";
280 };
281
282 qspi: spi@58003000 {
283 compatible = "st,stm32f469-qspi";
284 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
285 reg-names = "qspi", "qspi_mm";
286 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&rcc QSPI_K>;
288 resets = <&rcc QSPI_R>;
289 status = "disabled";
290 };
291
292 sdmmc1: sdmmc@58005000 {
293 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
294 arm,primecell-periphid = <0x00253180>;
295 reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
296 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
297 interrupt-names = "cmd_irq";
298 clocks = <&rcc SDMMC1_K>;
299 clock-names = "apb_pclk";
300 resets = <&rcc SDMMC1_R>;
301 cap-sd-highspeed;
302 cap-mmc-highspeed;
303 max-frequency = <120000000>;
304 status = "disabled";
305 };
306
307 sdmmc2: sdmmc@58007000 {
308 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
309 arm,primecell-periphid = <0x00253180>;
310 reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
311 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
312 interrupt-names = "cmd_irq";
313 clocks = <&rcc SDMMC2_K>;
314 clock-names = "apb_pclk";
315 resets = <&rcc SDMMC2_R>;
316 cap-sd-highspeed;
317 cap-mmc-highspeed;
318 max-frequency = <120000000>;
319 status = "disabled";
320 };
321
322 iwdg2: watchdog@5a002000 {
323 compatible = "st,stm32mp1-iwdg";
324 reg = <0x5a002000 0x400>;
325 secure-interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
327 clock-names = "pclk", "lsi";
328 status = "disabled";
329 };
330
331 usbphyc: usbphyc@5a006000 {
332 #address-cells = <1>;
333 #size-cells = <0>;
334 #clock-cells = <0>;
335 compatible = "st,stm32mp1-usbphyc";
336 reg = <0x5a006000 0x1000>;
337 clocks = <&rcc USBPHY_K>;
338 resets = <&rcc USBPHY_R>;
339 vdda1v1-supply = <&reg11>;
340 vdda1v8-supply = <&reg18>;
341 status = "disabled";
342
343 usbphyc_port0: usb-phy@0 {
344 #phy-cells = <0>;
345 reg = <0>;
346 };
347
348 usbphyc_port1: usb-phy@1 {
349 #phy-cells = <1>;
350 reg = <1>;
351 };
352 };
353
354 usart1: serial@5c000000 {
355 compatible = "st,stm32h7-uart";
356 reg = <0x5c000000 0x400>;
357 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&rcc USART1_K>;
359 resets = <&rcc USART1_R>;
360 status = "disabled";
361 };
362
363 spi6: spi@5c001000 {
364 #address-cells = <1>;
365 #size-cells = <0>;
366 compatible = "st,stm32h7-spi";
367 reg = <0x5c001000 0x400>;
368 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&rcc SPI6_K>;
370 resets = <&rcc SPI6_R>;
371 status = "disabled";
372 };
373
374 i2c4: i2c@5c002000 {
375 compatible = "st,stm32mp15-i2c";
376 reg = <0x5c002000 0x400>;
377 interrupt-names = "event", "error";
378 interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
379 <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&rcc I2C4_K>;
381 resets = <&rcc I2C4_R>;
382 #address-cells = <1>;
383 #size-cells = <0>;
384 st,syscfg-fmp = <&syscfg 0x4 0x8>;
385 wakeup-source;
386 status = "disabled";
387 };
388
389 iwdg1: watchdog@5c003000 {
390 compatible = "st,stm32mp1-iwdg";
391 reg = <0x5C003000 0x400>;
392 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
394 clock-names = "pclk", "lsi";
395 status = "disabled";
396 };
397
398 rtc: rtc@5c004000 {
399 compatible = "st,stm32mp1-rtc";
400 reg = <0x5c004000 0x400>;
401 clocks = <&rcc RTCAPB>, <&rcc RTC>;
402 clock-names = "pclk", "rtc_ck";
403 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
404 status = "disabled";
405 };
406
407 bsec: nvmem@5c005000 {
408 compatible = "st,stm32mp15-bsec";
409 reg = <0x5c005000 0x400>;
410 #address-cells = <1>;
411 #size-cells = <1>;
412 ts_cal1: calib@5c {
413 reg = <0x5c 0x2>;
414 };
415 ts_cal2: calib@5e {
416 reg = <0x5e 0x2>;
417 };
418 };
419
420 etzpc: etzpc@5c007000 {
421 compatible = "st,stm32-etzpc";
422 reg = <0x5C007000 0x400>;
423 clocks = <&rcc TZPC>;
424 status = "disabled";
425 secure-status = "okay";
426 };
427
428 stgen: stgen@5c008000 {
429 compatible = "st,stm32-stgen";
430 reg = <0x5C008000 0x1000>;
431 };
432
433 i2c6: i2c@5c009000 {
434 compatible = "st,stm32mp15-i2c";
435 reg = <0x5c009000 0x400>;
436 interrupt-names = "event", "error";
437 interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>,
438 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&rcc I2C6_K>;
440 resets = <&rcc I2C6_R>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443 st,syscfg-fmp = <&syscfg 0x4 0x20>;
444 wakeup-source;
445 status = "disabled";
446 };
447
448 tamp: tamp@5c00a000 {
449 compatible = "st,stm32-tamp", "simple-bus", "syscon", "simple-mfd";
450 reg = <0x5c00a000 0x400>;
451 secure-interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&rcc RTCAPB>;
453 };
454
455 /*
456 * Break node order to solve dependency probe issue between
457 * pinctrl and exti.
458 */
459 pinctrl: pin-controller@50002000 {
460 #address-cells = <1>;
461 #size-cells = <1>;
462 compatible = "st,stm32mp157-pinctrl";
463 ranges = <0 0x50002000 0xa400>;
464 interrupt-parent = <&exti>;
465 st,syscfg = <&exti 0x60 0xff>;
466 pins-are-numbered;
467
468 gpioa: gpio@50002000 {
469 gpio-controller;
470 #gpio-cells = <2>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
473 reg = <0x0 0x400>;
474 clocks = <&rcc GPIOA>;
475 st,bank-name = "GPIOA";
476 status = "disabled";
477 };
478
479 gpiob: gpio@50003000 {
480 gpio-controller;
481 #gpio-cells = <2>;
482 interrupt-controller;
483 #interrupt-cells = <2>;
484 reg = <0x1000 0x400>;
485 clocks = <&rcc GPIOB>;
486 st,bank-name = "GPIOB";
487 status = "disabled";
488 };
489
490 gpioc: gpio@50004000 {
491 gpio-controller;
492 #gpio-cells = <2>;
493 interrupt-controller;
494 #interrupt-cells = <2>;
495 reg = <0x2000 0x400>;
496 clocks = <&rcc GPIOC>;
497 st,bank-name = "GPIOC";
498 status = "disabled";
499 };
500
501 gpiod: gpio@50005000 {
502 gpio-controller;
503 #gpio-cells = <2>;
504 interrupt-controller;
505 #interrupt-cells = <2>;
506 reg = <0x3000 0x400>;
507 clocks = <&rcc GPIOD>;
508 st,bank-name = "GPIOD";
509 status = "disabled";
510 };
511
512 gpioe: gpio@50006000 {
513 gpio-controller;
514 #gpio-cells = <2>;
515 interrupt-controller;
516 #interrupt-cells = <2>;
517 reg = <0x4000 0x400>;
518 clocks = <&rcc GPIOE>;
519 st,bank-name = "GPIOE";
520 status = "disabled";
521 };
522
523 gpiof: gpio@50007000 {
524 gpio-controller;
525 #gpio-cells = <2>;
526 interrupt-controller;
527 #interrupt-cells = <2>;
528 reg = <0x5000 0x400>;
529 clocks = <&rcc GPIOF>;
530 st,bank-name = "GPIOF";
531 status = "disabled";
532 };
533
534 gpiog: gpio@50008000 {
535 gpio-controller;
536 #gpio-cells = <2>;
537 interrupt-controller;
538 #interrupt-cells = <2>;
539 reg = <0x6000 0x400>;
540 clocks = <&rcc GPIOG>;
541 st,bank-name = "GPIOG";
542 status = "disabled";
543 };
544
545 gpioh: gpio@50009000 {
546 gpio-controller;
547 #gpio-cells = <2>;
548 interrupt-controller;
549 #interrupt-cells = <2>;
550 reg = <0x7000 0x400>;
551 clocks = <&rcc GPIOH>;
552 st,bank-name = "GPIOH";
553 status = "disabled";
554 };
555
556 gpioi: gpio@5000a000 {
557 gpio-controller;
558 #gpio-cells = <2>;
559 interrupt-controller;
560 #interrupt-cells = <2>;
561 reg = <0x8000 0x400>;
562 clocks = <&rcc GPIOI>;
563 st,bank-name = "GPIOI";
564 status = "disabled";
565 };
566
567 gpioj: gpio@5000b000 {
568 gpio-controller;
569 #gpio-cells = <2>;
570 interrupt-controller;
571 #interrupt-cells = <2>;
572 reg = <0x9000 0x400>;
573 clocks = <&rcc GPIOJ>;
574 st,bank-name = "GPIOJ";
575 status = "disabled";
576 };
577
578 gpiok: gpio@5000c000 {
579 gpio-controller;
580 #gpio-cells = <2>;
581 interrupt-controller;
582 #interrupt-cells = <2>;
583 reg = <0xa000 0x400>;
584 clocks = <&rcc GPIOK>;
585 st,bank-name = "GPIOK";
586 status = "disabled";
587 };
588 };
589
590 pinctrl_z: pin-controller-z@54004000 {
591 #address-cells = <1>;
592 #size-cells = <1>;
593 compatible = "st,stm32mp157-z-pinctrl";
594 ranges = <0 0x54004000 0x400>;
595 pins-are-numbered;
596 interrupt-parent = <&exti>;
597 st,syscfg = <&exti 0x60 0xff>;
598
599 gpioz: gpio@54004000 {
600 gpio-controller;
601 #gpio-cells = <2>;
602 interrupt-controller;
603 #interrupt-cells = <2>;
604 reg = <0 0x400>;
605 clocks = <&rcc GPIOZ>;
606 st,bank-name = "GPIOZ";
607 st,bank-ioport = <11>;
608 status = "disabled";
609 };
610 };
611 };
612};