| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 1 | /* |
| Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __CORTEX_ARES_H__ |
| 8 | #define __CORTEX_ARES_H__ |
| 9 | |
| 10 | /* Cortex-ARES MIDR for revision 0 */ |
| 11 | #define CORTEX_ARES_MIDR 0x410fd0c0 |
| 12 | |
| 13 | /******************************************************************************* |
| 14 | * CPU Extended Control register specific definitions. |
| 15 | ******************************************************************************/ |
| 16 | #define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 17 | #define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 18 | |
| 19 | /* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */ |
| 20 | #define CORTEX_ARES_CORE_PWRDN_EN_MASK 0x1 |
| 21 | |
| Dimitris Papastamos | 89736dd | 2018-02-13 11:28:02 +0000 | [diff] [blame] | 22 | #define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4) |
| 23 | |
| 24 | #define CORTEX_ARES_AMU_NR_COUNTERS U(5) |
| 25 | #define CORTEX_ARES_AMU_GROUP0_MASK U(0x1f) |
| 26 | |
| Dimitris Papastamos | 7ca21db | 2018-03-26 16:46:01 +0100 | [diff] [blame] | 27 | /* Instruction patching registers */ |
| 28 | #define CPUPSELR_EL3 S3_6_C15_C8_0 |
| 29 | #define CPUPCR_EL3 S3_6_C15_C8_1 |
| 30 | #define CPUPOR_EL3 S3_6_C15_C8_2 |
| 31 | #define CPUPMR_EL3 S3_6_C15_C8_3 |
| 32 | |
| Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 33 | #endif /* __CORTEX_ARES_H__ */ |