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Antonio Nino Diaz3c817f42018-03-21 10:49:27 +00001/*
Alexei Fedorov9074dea2019-08-20 15:22:44 +01002 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00006#ifndef SMCCC_MACROS_S
7#define SMCCC_MACROS_S
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +00008
9#include <arch.h>
10
11/*
12 * Macro to save the General purpose registers (r0 - r12), the banked
13 * spsr, lr, sp registers and the `scr` register to the SMC context on entry
14 * due a SMC call. The `lr` of the current mode (monitor) is expected to be
15 * already saved. The `sp` must point to the `smc_ctx_t` to save to.
16 * Additionally, also save the 'pmcr' register as this is updated whilst
17 * executing in the secure world.
18 */
19 .macro smccc_save_gp_mode_regs
20 /* Save r0 - r12 in the SMC context */
21 stm sp, {r0-r12}
22 mov r0, sp
23 add r0, r0, #SMC_CTX_SP_USR
24
25#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION)
26 /* Must be in secure state to restore Monitor mode */
27 ldcopr r4, SCR
28 bic r2, r4, #SCR_NS_BIT
29 stcopr r2, SCR
30 isb
31
32 cps #MODE32_sys
33 stm r0!, {sp, lr}
34
35 cps #MODE32_irq
36 mrs r2, spsr
37 stm r0!, {r2, sp, lr}
38
39 cps #MODE32_fiq
40 mrs r2, spsr
41 stm r0!, {r2, sp, lr}
42
43 cps #MODE32_svc
44 mrs r2, spsr
45 stm r0!, {r2, sp, lr}
46
47 cps #MODE32_abt
48 mrs r2, spsr
49 stm r0!, {r2, sp, lr}
50
51 cps #MODE32_und
52 mrs r2, spsr
53 stm r0!, {r2, sp, lr}
54
55 /* lr_mon is already saved by caller */
56 cps #MODE32_mon
57 mrs r2, spsr
58 stm r0!, {r2}
59
60 stcopr r4, SCR
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +000061#else
62 /* Save the banked registers including the current SPSR and LR */
63 mrs r4, sp_usr
64 mrs r5, lr_usr
65 mrs r6, spsr_irq
66 mrs r7, sp_irq
67 mrs r8, lr_irq
68 mrs r9, spsr_fiq
69 mrs r10, sp_fiq
70 mrs r11, lr_fiq
71 mrs r12, spsr_svc
72 stm r0!, {r4-r12}
73
74 mrs r4, sp_svc
75 mrs r5, lr_svc
76 mrs r6, spsr_abt
77 mrs r7, sp_abt
78 mrs r8, lr_abt
79 mrs r9, spsr_und
80 mrs r10, sp_und
81 mrs r11, lr_und
82 mrs r12, spsr
83 stm r0!, {r4-r12}
84 /* lr_mon is already saved by caller */
85
86 ldcopr r4, SCR
Alexei Fedorov9074dea2019-08-20 15:22:44 +010087
88#if ARM_ARCH_MAJOR > 7
89 /*
90 * Check if earlier initialization of SDCR.SCCD to 1
91 * failed, meaning that ARMv8-PMU is not implemented,
92 * cycle counting is not disabled and PMCR should be
93 * saved in Non-secure context.
94 */
95 ldcopr r5, SDCR
96 tst r5, #SDCR_SCCD_BIT
97 bne 1f
98#endif
99 /* Secure Cycle Counter is not disabled */
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +0000100#endif
Alexei Fedorov9074dea2019-08-20 15:22:44 +0100101 ldcopr r5, PMCR
102
103 /* Check caller's security state */
104 tst r4, #SCR_NS_BIT
105 beq 2f
106
107 /* Save PMCR if called from Non-secure state */
108 str r5, [sp, #SMC_CTX_PMCR]
109
110 /* Disable cycle counter when event counting is prohibited */
1112: orr r5, r5, #PMCR_DP_BIT
112 stcopr r5, PMCR
113 isb
1141: str r4, [sp, #SMC_CTX_SCR]
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +0000115 .endm
116
117/*
118 * Macro to restore the `smc_ctx_t`, which includes the General purpose
119 * registers and banked mode registers, and exit from the monitor mode.
120 * r0 must point to the `smc_ctx_t` to restore from.
121 */
122 .macro monitor_exit
123 /*
124 * Save the current sp and restore the smc context
125 * pointer to sp which will be used for handling the
126 * next SMC.
127 */
128 str sp, [r0, #SMC_CTX_SP_MON]
129 mov sp, r0
130
131 /*
132 * Restore SCR first so that we access the right banked register
133 * when the other mode registers are restored.
134 */
135 ldr r1, [r0, #SMC_CTX_SCR]
136 stcopr r1, SCR
137 isb
138
139 /*
Alexei Fedorov9074dea2019-08-20 15:22:44 +0100140 * Restore PMCR when returning to Non-secure state
141 */
142 tst r1, #SCR_NS_BIT
143 beq 2f
144
145 /*
146 * Back to Non-secure state
147 */
148#if ARM_ARCH_MAJOR > 7
149 /*
150 * Check if earlier initialization SDCR.SCCD to 1
151 * failed, meaning that ARMv8-PMU is not implemented and
152 * PMCR should be restored from Non-secure context.
153 */
154 ldcopr r1, SDCR
155 tst r1, #SDCR_SCCD_BIT
156 bne 2f
157#endif
158 /*
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +0000159 * Restore the PMCR register.
160 */
161 ldr r1, [r0, #SMC_CTX_PMCR]
162 stcopr r1, PMCR
Alexei Fedorov9074dea2019-08-20 15:22:44 +01001632:
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +0000164 /* Restore the banked registers including the current SPSR */
165 add r1, r0, #SMC_CTX_SP_USR
166
167#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION)
168 /* Must be in secure state to restore Monitor mode */
169 ldcopr r4, SCR
170 bic r2, r4, #SCR_NS_BIT
171 stcopr r2, SCR
172 isb
173
174 cps #MODE32_sys
175 ldm r1!, {sp, lr}
176
177 cps #MODE32_irq
178 ldm r1!, {r2, sp, lr}
179 msr spsr_fsxc, r2
180
181 cps #MODE32_fiq
182 ldm r1!, {r2, sp, lr}
183 msr spsr_fsxc, r2
184
185 cps #MODE32_svc
186 ldm r1!, {r2, sp, lr}
187 msr spsr_fsxc, r2
188
189 cps #MODE32_abt
190 ldm r1!, {r2, sp, lr}
191 msr spsr_fsxc, r2
192
193 cps #MODE32_und
194 ldm r1!, {r2, sp, lr}
195 msr spsr_fsxc, r2
196
197 cps #MODE32_mon
198 ldm r1!, {r2}
199 msr spsr_fsxc, r2
200
201 stcopr r4, SCR
202 isb
203#else
204 ldm r1!, {r4-r12}
205 msr sp_usr, r4
206 msr lr_usr, r5
207 msr spsr_irq, r6
208 msr sp_irq, r7
209 msr lr_irq, r8
210 msr spsr_fiq, r9
211 msr sp_fiq, r10
212 msr lr_fiq, r11
213 msr spsr_svc, r12
214
215 ldm r1!, {r4-r12}
216 msr sp_svc, r4
217 msr lr_svc, r5
218 msr spsr_abt, r6
219 msr sp_abt, r7
220 msr lr_abt, r8
221 msr spsr_und, r9
222 msr sp_und, r10
223 msr lr_und, r11
224 /*
225 * Use the `_fsxc` suffix explicitly to instruct the assembler
226 * to update all the 32 bits of SPSR. Else, by default, the
227 * assembler assumes `_fc` suffix which only modifies
228 * f->[31:24] and c->[7:0] bits of SPSR.
229 */
230 msr spsr_fsxc, r12
231#endif
232
233 /* Restore the LR */
234 ldr lr, [r0, #SMC_CTX_LR_MON]
235
236 /* Restore the rest of the general purpose registers */
237 ldm r0, {r0-r12}
238 eret
239 .endm
240
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000241#endif /* SMCCC_MACROS_S */