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developer550bf5e2016-07-11 16:05:23 +08001#
dp-arm230011c2017-03-07 11:02:47 +00002# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
developer550bf5e2016-07-11 16:05:23 +08003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
developer550bf5e2016-07-11 16:05:23 +08005#
6
7MTK_PLAT := plat/mediatek
8MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
9
10# Add OEM customized codes
11OEMS := true
12MTK_SIP_KERNEL_BOOT_ENABLE := 1
13
14
15ifneq (${OEMS},none)
16 OEMS_INCLUDES := -I${MTK_PLAT}/common/custom/
17 OEMS_SOURCES := ${MTK_PLAT}/common/custom/oem_svc.c
18endif
19
20PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
21 -I${MTK_PLAT}/common/drivers/uart \
22 -I${MTK_PLAT_SOC}/ \
23 -I${MTK_PLAT_SOC}/drivers/timer/ \
24 -I${MTK_PLAT_SOC}/include/ \
25 -Iinclude/plat/arm/common/ \
26 -Iinclude/common/tbbr/ \
27 ${OEMS_INCLUDES}
28
29PLAT_BL_COMMON_SOURCES := lib/aarch64/xlat_tables.c \
developer550bf5e2016-07-11 16:05:23 +080030 plat/common/plat_gic.c
31
32BL31_SOURCES += drivers/arm/cci/cci.c \
33 drivers/delay_timer/generic_delay_timer.c \
34 drivers/arm/gic/common/gic_common.c \
35 drivers/arm/gic/v2/gicv2_main.c \
36 drivers/arm/gic/v2/gicv2_helpers.c \
37 plat/common/plat_gicv2.c \
38 drivers/console/console.S \
39 drivers/delay_timer/delay_timer.c \
40 lib/cpus/aarch64/cortex_a53.S \
developer550bf5e2016-07-11 16:05:23 +080041 ${MTK_PLAT_SOC}/bl31_plat_setup.c \
42 ${MTK_PLAT_SOC}/plat_mt_gic.c \
43 ${MTK_PLAT}/common/mtk_sip_svc.c \
44 ${MTK_PLAT}/common/mtk_plat_common.c \
45 ${MTK_PLAT}/common/drivers/uart/8250_console.S \
46 ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
47 ${MTK_PLAT_SOC}/drivers/timer/mt_cpuxgpt.c \
developer550bf5e2016-07-11 16:05:23 +080048 ${MTK_PLAT_SOC}/plat_delay_timer.c \
49 ${MTK_PLAT_SOC}/plat_pm.c \
50 ${MTK_PLAT_SOC}/plat_topology.c \
51 ${MTK_PLAT_SOC}/power_tracer.c \
52 ${MTK_PLAT_SOC}/scu.c \
53 ${OEMS_SOURCES}
54
55# Flag used by the MTK_platform port to determine the version of ARM GIC
56# architecture to use for interrupt management in EL3.
57ARM_GIC_ARCH := 2
58$(eval $(call add_define,ARM_GIC_ARCH))
59
60# Enable workarounds for selected Cortex-A53 erratas.
61ERRATA_A53_826319 := 1
62ERRATA_A53_836870 := 1
63
64# indicate the reset vector address can be programmed
65PROGRAMMABLE_RESET_ADDRESS := 1
66
67$(eval $(call add_define,MTK_SIP_KERNEL_BOOT_ENABLE))
68
David Cunadoc5b0c0f2017-10-31 23:19:21 +000069# Do not enable SVE
70ENABLE_SVE_FOR_NS := 0