| Varun Wadekar | b374103 | 2017-09-25 13:27:45 -0700 | [diff] [blame] | 1 | /* |
| steven kao | 05ee582 | 2018-01-02 19:07:00 -0800 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
| Varun Wadekar | 2909fa3 | 2020-01-09 08:52:10 -0800 | [diff] [blame] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
| Varun Wadekar | b374103 | 2017-09-25 13:27:45 -0700 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| Varun Wadekar | 2909fa3 | 2020-01-09 08:52:10 -0800 | [diff] [blame] | 8 | #ifndef BPMP_IPC_H |
| 9 | #define BPMP_IPC_H |
| Varun Wadekar | b374103 | 2017-09-25 13:27:45 -0700 | [diff] [blame] | 10 | |
| Ambroise Vincent | ffbf32a | 2019-03-28 09:01:18 +0000 | [diff] [blame] | 11 | #include <lib/utils_def.h> |
| Varun Wadekar | b374103 | 2017-09-25 13:27:45 -0700 | [diff] [blame] | 12 | #include <stdbool.h> |
| 13 | #include <stdint.h> |
| Varun Wadekar | b374103 | 2017-09-25 13:27:45 -0700 | [diff] [blame] | 14 | |
| 15 | /** |
| 16 | * Currently supported reset identifiers |
| 17 | */ |
| 18 | #define TEGRA_RESET_ID_XUSB_PADCTL U(114) |
| 19 | #define TEGRA_RESET_ID_GPCDMA U(70) |
| 20 | |
| 21 | /** |
| steven kao | 05ee582 | 2018-01-02 19:07:00 -0800 | [diff] [blame] | 22 | * Clock identifier for the SE device |
| 23 | */ |
| 24 | #define TEGRA_CLK_SE U(124) |
| 25 | |
| 26 | /** |
| Varun Wadekar | b374103 | 2017-09-25 13:27:45 -0700 | [diff] [blame] | 27 | * Function to initialise the IPC with the bpmp |
| 28 | */ |
| 29 | int32_t tegra_bpmp_ipc_init(void); |
| 30 | |
| 31 | /** |
| 32 | * Handler to reset a module |
| 33 | */ |
| 34 | int32_t tegra_bpmp_ipc_reset_module(uint32_t rst_id); |
| 35 | |
| steven kao | 05ee582 | 2018-01-02 19:07:00 -0800 | [diff] [blame] | 36 | /** |
| 37 | * Handler to enable clock to a module. Only SE device is |
| 38 | * supported for now. |
| 39 | */ |
| 40 | int tegra_bpmp_ipc_enable_clock(uint32_t clk_id); |
| 41 | |
| 42 | /** |
| 43 | * Handler to disable clock to a module. Only SE device is |
| 44 | * supported for now. |
| 45 | */ |
| 46 | int tegra_bpmp_ipc_disable_clock(uint32_t clk_id); |
| 47 | |
| Varun Wadekar | 2909fa3 | 2020-01-09 08:52:10 -0800 | [diff] [blame] | 48 | #endif /* BPMP_IPC_H */ |