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Soby Mathew991d42c2015-06-29 16:30:12 +01001/*
Soby Mathew3a9e8bf2015-05-05 16:33:16 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Soby Mathew991d42c2015-06-29 16:30:12 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <assert.h>
32#include <bl_common.h>
33#include <arch.h>
34#include <arch_helpers.h>
35#include <context.h>
36#include <context_mgmt.h>
37#include <cpu_data.h>
38#include <debug.h>
39#include <platform.h>
40#include <runtime_svc.h>
41#include <stddef.h>
42#include "psci_private.h"
43
Soby Mathew991d42c2015-06-29 16:30:12 +010044/*******************************************************************************
Soby Mathew85dbf5a2015-04-07 12:16:56 +010045 * This function does generic and platform specific operations after a wake-up
46 * from standby/retention states at multiple power levels.
Soby Mathew991d42c2015-06-29 16:30:12 +010047 ******************************************************************************/
Soby Mathew85dbf5a2015-04-07 12:16:56 +010048static void psci_suspend_to_standby_finisher(unsigned int cpu_idx,
49 psci_power_state_t *state_info,
50 unsigned int end_pwrlvl)
Soby Mathew991d42c2015-06-29 16:30:12 +010051{
Soby Mathew85dbf5a2015-04-07 12:16:56 +010052 psci_acquire_pwr_domain_locks(end_pwrlvl,
53 cpu_idx);
Soby Mathew991d42c2015-06-29 16:30:12 +010054
Soby Mathew85dbf5a2015-04-07 12:16:56 +010055 /*
56 * Plat. management: Allow the platform to do operations
57 * on waking up from retention.
58 */
59 psci_plat_pm_ops->pwr_domain_suspend_finish(state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +010060
Soby Mathew85dbf5a2015-04-07 12:16:56 +010061 /*
62 * Set the requested and target state of this CPU and all the higher
63 * power domain levels for this CPU to run.
64 */
65 psci_set_pwr_domains_to_run(end_pwrlvl);
Soby Mathew991d42c2015-06-29 16:30:12 +010066
Soby Mathew85dbf5a2015-04-07 12:16:56 +010067 psci_release_pwr_domain_locks(end_pwrlvl,
68 cpu_idx);
Soby Mathew991d42c2015-06-29 16:30:12 +010069}
70
71/*******************************************************************************
Soby Mathew85dbf5a2015-04-07 12:16:56 +010072 * This function does generic and platform specific suspend to power down
73 * operations.
Soby Mathew991d42c2015-06-29 16:30:12 +010074 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010075static void psci_suspend_to_pwrdown_start(unsigned int end_pwrlvl,
Soby Mathew85dbf5a2015-04-07 12:16:56 +010076 entry_point_info_t *ep,
77 psci_power_state_t *state_info)
Soby Mathew991d42c2015-06-29 16:30:12 +010078{
Achin Gupta9a0ff9b2015-09-07 20:43:27 +010079 unsigned int max_off_lvl = psci_find_max_off_lvl(state_info);
80
Soby Mathew85dbf5a2015-04-07 12:16:56 +010081 /* Save PSCI target power level for the suspend finisher handler */
82 psci_set_suspend_pwrlvl(end_pwrlvl);
Soby Mathew991d42c2015-06-29 16:30:12 +010083
Soby Mathew85dbf5a2015-04-07 12:16:56 +010084 /*
85 * Flush the target power level as it will be accessed on power up with
86 * Data cache disabled.
87 */
88 flush_cpu_data(psci_svc_cpu_data.target_pwrlvl);
Soby Mathew991d42c2015-06-29 16:30:12 +010089
Soby Mathew85dbf5a2015-04-07 12:16:56 +010090 /*
91 * Call the cpu suspend handler registered by the Secure Payload
92 * Dispatcher to let it do any book-keeping. If the handler encounters an
93 * error, it's expected to assert within
94 */
95 if (psci_spd_pm && psci_spd_pm->svc_suspend)
Achin Gupta9a0ff9b2015-09-07 20:43:27 +010096 psci_spd_pm->svc_suspend(max_off_lvl);
Soby Mathew991d42c2015-06-29 16:30:12 +010097
Soby Mathew85dbf5a2015-04-07 12:16:56 +010098 /*
99 * Store the re-entry information for the non-secure world.
100 */
101 cm_init_my_context(ep);
Soby Mathew991d42c2015-06-29 16:30:12 +0100102
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100103 /*
104 * Arch. management. Perform the necessary steps to flush all
105 * cpu caches. Currently we assume that the power level correspond
106 * the cache level.
107 * TODO : Introduce a mechanism to query the cache level to flush
108 * and the cpu-ops power down to perform from the platform.
109 */
Achin Gupta9a0ff9b2015-09-07 20:43:27 +0100110 psci_do_pwrdown_cache_maintenance(max_off_lvl);
Soby Mathew991d42c2015-06-29 16:30:12 +0100111}
112
113/*******************************************************************************
Soby Mathew991d42c2015-06-29 16:30:12 +0100114 * Top level handler which is called when a cpu wants to suspend its execution.
Soby Mathew3a9e8bf2015-05-05 16:33:16 +0100115 * It is assumed that along with suspending the cpu power domain, power domains
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100116 * at higher levels until the target power level will be suspended as well. It
117 * coordinates with the platform to negotiate the target state for each of
118 * the power domain level till the target power domain level. It then performs
119 * generic, architectural, platform setup and state management required to
120 * suspend that power domain level and power domain levels below it.
121 * e.g. For a cpu that's to be suspended, it could mean programming the
122 * power controller whereas for a cluster that's to be suspended, it will call
123 * the platform specific code which will disable coherency at the interconnect
124 * level if the cpu is the last in the cluster and also the program the power
125 * controller.
Soby Mathew991d42c2015-06-29 16:30:12 +0100126 *
127 * All the required parameter checks are performed at the beginning and after
Soby Mathew6b8b3022015-06-30 11:00:24 +0100128 * the state transition has been done, no further error is expected and it is
129 * not possible to undo any of the actions taken beyond that point.
Soby Mathew991d42c2015-06-29 16:30:12 +0100130 ******************************************************************************/
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100131void psci_cpu_suspend_start(entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100132 unsigned int end_pwrlvl,
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100133 psci_power_state_t *state_info,
134 unsigned int is_power_down_state)
Soby Mathew991d42c2015-06-29 16:30:12 +0100135{
136 int skip_wfi = 0;
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100137 unsigned int idx = plat_my_core_pos();
Soby Mathew991d42c2015-06-29 16:30:12 +0100138
139 /*
140 * This function must only be called on platforms where the
141 * CPU_SUSPEND platform hooks have been implemented.
142 */
Soby Mathew3a9e8bf2015-05-05 16:33:16 +0100143 assert(psci_plat_pm_ops->pwr_domain_suspend &&
144 psci_plat_pm_ops->pwr_domain_suspend_finish);
Soby Mathew991d42c2015-06-29 16:30:12 +0100145
146 /*
Soby Mathew3a9e8bf2015-05-05 16:33:16 +0100147 * This function acquires the lock corresponding to each power
Soby Mathew991d42c2015-06-29 16:30:12 +0100148 * level so that by the time all locks are taken, the system topology
149 * is snapshot and state management can be done safely.
150 */
Soby Mathew9d754f62015-04-08 17:42:06 +0100151 psci_acquire_pwr_domain_locks(end_pwrlvl,
152 idx);
Soby Mathew991d42c2015-06-29 16:30:12 +0100153
154 /*
155 * We check if there are any pending interrupts after the delay
156 * introduced by lock contention to increase the chances of early
157 * detection that a wake-up interrupt has fired.
158 */
159 if (read_isr_el1()) {
160 skip_wfi = 1;
161 goto exit;
162 }
163
164 /*
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100165 * This function is passed the requested state info and
166 * it returns the negotiated state info for each power level upto
167 * the end level specified.
Soby Mathew991d42c2015-06-29 16:30:12 +0100168 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100169 psci_do_state_coordination(end_pwrlvl, state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +0100170
Sandrine Bailleux574d6852015-06-11 10:46:48 +0100171 if (is_power_down_state)
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100172 psci_suspend_to_pwrdown_start(end_pwrlvl, ep, state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +0100173
Soby Mathew6b8b3022015-06-30 11:00:24 +0100174 /*
175 * Plat. management: Allow the platform to perform the
176 * necessary actions to turn off this cpu e.g. set the
177 * platform defined mailbox with the psci entrypoint,
178 * program the power controller etc.
179 */
Sandrine Bailleux574d6852015-06-11 10:46:48 +0100180 psci_plat_pm_ops->pwr_domain_suspend(state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +0100181
182exit:
183 /*
Soby Mathew3a9e8bf2015-05-05 16:33:16 +0100184 * Release the locks corresponding to each power level in the
Soby Mathew991d42c2015-06-29 16:30:12 +0100185 * reverse order to which they were acquired.
186 */
Soby Mathew9d754f62015-04-08 17:42:06 +0100187 psci_release_pwr_domain_locks(end_pwrlvl,
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100188 idx);
189 if (skip_wfi)
190 return;
191
192 if (is_power_down_state)
Soby Mathew991d42c2015-06-29 16:30:12 +0100193 psci_power_down_wfi();
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100194
195 /*
196 * We will reach here if only retention/standby states have been
197 * requested at multiple power levels. This means that the cpu
198 * context will be preserved.
199 */
200 wfi();
201
202 /*
203 * After we wake up from context retaining suspend, call the
204 * context retaining suspend finisher.
205 */
206 psci_suspend_to_standby_finisher(idx, state_info, end_pwrlvl);
Soby Mathew991d42c2015-06-29 16:30:12 +0100207}
208
209/*******************************************************************************
Soby Mathew3a9e8bf2015-05-05 16:33:16 +0100210 * The following functions finish an earlier suspend request. They
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100211 * are called by the common finisher routine in psci_common.c. The `state_info`
212 * is the psci_power_state from which this CPU has woken up from.
Soby Mathew991d42c2015-06-29 16:30:12 +0100213 ******************************************************************************/
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100214void psci_cpu_suspend_finish(unsigned int cpu_idx,
215 psci_power_state_t *state_info)
Soby Mathew991d42c2015-06-29 16:30:12 +0100216{
Soby Mathew011ca182015-07-29 17:05:03 +0100217 unsigned long long counter_freq;
Achin Gupta9a0ff9b2015-09-07 20:43:27 +0100218 unsigned int max_off_lvl;
Soby Mathew991d42c2015-06-29 16:30:12 +0100219
Soby Mathew991d42c2015-06-29 16:30:12 +0100220 /* Ensure we have been woken up from a suspended state */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100221 assert(psci_get_aff_info_state() == AFF_STATE_ON && is_local_state_off(\
222 state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]));
Soby Mathew991d42c2015-06-29 16:30:12 +0100223
224 /*
225 * Plat. management: Perform the platform specific actions
226 * before we change the state of the cpu e.g. enabling the
227 * gic or zeroing the mailbox register. If anything goes
228 * wrong then assert as there is no way to recover from this
229 * situation.
230 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100231 psci_plat_pm_ops->pwr_domain_suspend_finish(state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +0100232
233 /*
234 * Arch. management: Enable the data cache, manage stack memory and
235 * restore the stashed EL3 architectural context from the 'cpu_context'
236 * structure for this cpu.
237 */
238 psci_do_pwrup_cache_maintenance();
239
240 /* Re-init the cntfrq_el0 register */
241 counter_freq = plat_get_syscnt_freq();
242 write_cntfrq_el0(counter_freq);
243
244 /*
245 * Call the cpu suspend finish handler registered by the Secure Payload
246 * Dispatcher to let it do any bookeeping. If the handler encounters an
247 * error, it's expected to assert within
248 */
249 if (psci_spd_pm && psci_spd_pm->svc_suspend) {
Achin Gupta9a0ff9b2015-09-07 20:43:27 +0100250 max_off_lvl = psci_find_max_off_lvl(state_info);
251 assert (max_off_lvl != PSCI_INVALID_PWR_LVL);
252 psci_spd_pm->svc_suspend_finish(max_off_lvl);
Soby Mathew991d42c2015-06-29 16:30:12 +0100253 }
254
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100255 /* Invalidate the suspend level for the cpu */
Soby Mathew011ca182015-07-29 17:05:03 +0100256 psci_set_suspend_pwrlvl(PSCI_INVALID_PWR_LVL);
Soby Mathew991d42c2015-06-29 16:30:12 +0100257
258 /*
259 * Generic management: Now we just need to retrieve the
260 * information that we had stashed away during the suspend
261 * call to set this cpu on its way.
262 */
263 cm_prepare_el3_exit(NON_SECURE);
Soby Mathew991d42c2015-06-29 16:30:12 +0100264}