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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <arch_helpers.h>
33#include <assert.h>
34#include <bl31.h>
35#include <bl_common.h>
36#include <console.h>
37#include <cortex_a57.h>
38#include <cortex_a53.h>
39#include <debug.h>
Varun Wadekar7a269e22015-06-10 14:04:32 +053040#include <errno.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053041#include <memctrl.h>
42#include <mmio.h>
43#include <platform.h>
44#include <platform_def.h>
45#include <stddef.h>
46#include <tegra_private.h>
47
48/*******************************************************************************
49 * Declarations of linker defined symbols which will help us find the layout
50 * of trusted SRAM
51 ******************************************************************************/
52extern unsigned long __RO_START__;
53extern unsigned long __RO_END__;
54extern unsigned long __BL31_END__;
55
56#if USE_COHERENT_MEM
57extern unsigned long __COHERENT_RAM_START__;
58extern unsigned long __COHERENT_RAM_END__;
59#endif
60
61extern uint64_t tegra_bl31_phys_base;
62
63/*
64 * The next 3 constants identify the extents of the code, RO data region and the
65 * limit of the BL3-1 image. These addresses are used by the MMU setup code and
66 * therefore they must be page-aligned. It is the responsibility of the linker
67 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
68 * refer to page-aligned addresses.
69 */
70#define BL31_RO_BASE (unsigned long)(&__RO_START__)
71#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
72#define BL31_END (unsigned long)(&__BL31_END__)
73
74#if USE_COHERENT_MEM
75/*
76 * The next 2 constants identify the extents of the coherent memory region.
77 * These addresses are used by the MMU setup code and therefore they must be
78 * page-aligned. It is the responsibility of the linker script to ensure that
79 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
80 * refer to page-aligned addresses.
81 */
82#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
83#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
84#endif
85
Varun Wadekar52a15982015-06-05 12:57:27 +053086static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
Varun Wadekarb316e242015-05-19 16:48:04 +053087static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
88 (uint64_t)TZDRAM_SIZE, (uintptr_t)NULL
89};
90
91/*******************************************************************************
92 * This variable holds the non-secure image entry address
93 ******************************************************************************/
94extern uint64_t ns_image_entrypoint;
95
96/*******************************************************************************
97 * Return a pointer to the 'entry_point_info' structure of the next image for
98 * security state specified. BL33 corresponds to the non-secure image type
99 * while BL32 corresponds to the secure image type.
100 ******************************************************************************/
101entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
102{
103 if (type == NON_SECURE)
104 return &bl33_image_ep_info;
105
Varun Wadekar52a15982015-06-05 12:57:27 +0530106 if (type == SECURE)
107 return &bl32_image_ep_info;
108
Varun Wadekarb316e242015-05-19 16:48:04 +0530109 return NULL;
110}
111
112/*******************************************************************************
113 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
114 * passes this platform specific information.
115 ******************************************************************************/
116plat_params_from_bl2_t *bl31_get_plat_params(void)
117{
118 return &plat_bl31_params_from_bl2;
119}
120
121/*******************************************************************************
122 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
123 * info.
124 ******************************************************************************/
125void bl31_early_platform_setup(bl31_params_t *from_bl2,
126 void *plat_params_from_bl2)
127{
128 plat_params_from_bl2_t *plat_params =
129 (plat_params_from_bl2_t *)plat_params_from_bl2;
130
131 /*
132 * Configure the UART port to be used as the console
133 */
134 console_init(TEGRA_BOOT_UART_BASE, TEGRA_BOOT_UART_CLK_IN_HZ,
135 TEGRA_CONSOLE_BAUDRATE);
136
137 /* Initialise crash console */
138 plat_crash_console_init();
139
140 /*
Varun Wadekar52a15982015-06-05 12:57:27 +0530141 * Copy BL3-3, BL3-2 entry point information.
Varun Wadekarb316e242015-05-19 16:48:04 +0530142 * They are stored in Secure RAM, in BL2's address space.
143 */
144 bl33_image_ep_info = *from_bl2->bl33_ep_info;
Varun Wadekar52a15982015-06-05 12:57:27 +0530145 bl32_image_ep_info = *from_bl2->bl32_ep_info;
Varun Wadekarb316e242015-05-19 16:48:04 +0530146
147 /*
148 * Parse platform specific parameters - TZDRAM aperture size and
149 * pointer to BL32 params.
150 */
151 if (plat_params) {
152 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
153 plat_bl31_params_from_bl2.bl32_params = plat_params->bl32_params;
154 }
155}
156
157/*******************************************************************************
158 * Initialize the gic, configure the SCR.
159 ******************************************************************************/
160void bl31_platform_setup(void)
161{
162 uint32_t tmp_reg;
163
164 /*
165 * Setup secondary CPU POR infrastructure.
166 */
167 plat_secondary_setup();
168
169 /*
170 * Initial Memory Controller configuration.
171 */
172 tegra_memctrl_setup();
173
174 /*
175 * Do initial security configuration to allow DRAM/device access.
176 */
177 tegra_memctrl_tzdram_setup(tegra_bl31_phys_base,
178 plat_bl31_params_from_bl2.tzdram_size);
179
180 /* Set the next EL to be AArch64 */
181 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT;
182 write_scr(tmp_reg);
183
184 /* Initialize the gic cpu and distributor interfaces */
185 tegra_gic_setup();
186}
187
188/*******************************************************************************
189 * Perform the very early platform specific architectural setup here. At the
190 * moment this only intializes the mmu in a quick and dirty way.
191 ******************************************************************************/
192void bl31_plat_arch_setup(void)
193{
194 unsigned long bl31_base_pa = tegra_bl31_phys_base;
195 unsigned long total_base = bl31_base_pa;
196 unsigned long total_size = TZDRAM_END - BL31_RO_BASE;
197 unsigned long ro_start = bl31_base_pa;
198 unsigned long ro_size = BL31_RO_LIMIT - BL31_RO_BASE;
199 unsigned long coh_start = 0;
200 unsigned long coh_size = 0;
201 const mmap_region_t *plat_mmio_map = NULL;
202
203#if USE_COHERENT_MEM
204 coh_start = total_base + (BL31_COHERENT_RAM_BASE - BL31_RO_BASE);
205 coh_size = BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE;
206#endif
207
208 /* add memory regions */
209 mmap_add_region(total_base, total_base,
210 total_size,
211 MT_MEMORY | MT_RW | MT_SECURE);
212 mmap_add_region(ro_start, ro_start,
213 ro_size,
214 MT_MEMORY | MT_RO | MT_SECURE);
215#if USE_COHERENT_MEM
216 mmap_add_region(coh_start, coh_start,
217 coh_size,
218 MT_DEVICE | MT_RW | MT_SECURE);
219#endif
220
221 /* add MMIO space */
222 plat_mmio_map = plat_get_mmio_map();
223 if (plat_mmio_map)
224 mmap_add(plat_mmio_map);
225 else
226 WARN("MMIO map not available\n");
227
228 /* set up translation tables */
229 init_xlat_tables();
230
231 /* enable the MMU */
232 enable_mmu_el3(0);
233}
Varun Wadekar7a269e22015-06-10 14:04:32 +0530234
235/*******************************************************************************
236 * Check if the given NS DRAM range is valid
237 ******************************************************************************/
238int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
239{
240 uint64_t end = base + size_in_bytes - 1;
241
242 /*
243 * Check if the NS DRAM address is valid
244 */
245 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) ||
246 (base >= end)) {
247 ERROR("NS address is out-of-bounds!\n");
248 return -EFAULT;
249 }
250
251 /*
252 * TZDRAM aperture contains the BL31 and BL32 images, so we need
253 * to check if the NS DRAM range overlaps the TZDRAM aperture.
254 */
255 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) {
256 ERROR("NS address overlaps TZDRAM!\n");
257 return -ENOTSUP;
258 }
259
260 /* valid NS address */
261 return 0;
262}