| Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef MISC_REGS_H |
| 8 | #define MISC_REGS_H |
| Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 9 | |
| 10 | /* CRU */ |
| 11 | #define CRU_DPLL_CON0 0x40 |
| 12 | #define CRU_DPLL_CON1 0x44 |
| 13 | #define CRU_DPLL_CON2 0x48 |
| 14 | #define CRU_DPLL_CON3 0x4c |
| 15 | #define CRU_DPLL_CON4 0x50 |
| 16 | #define CRU_DPLL_CON5 0x54 |
| 17 | |
| 18 | /* CRU_PLL_CON3 */ |
| 19 | #define PLL_SLOW_MODE 0 |
| 20 | #define PLL_NORMAL_MODE 1 |
| 21 | #define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8)) |
| 22 | #define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0)) |
| 23 | |
| 24 | /* PMU CRU */ |
| 25 | #define PMU_CRU_GATEDIS_CON0 0x130 |
| 26 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 27 | #endif /* MISC_REGS_H */ |