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git01.mediatek.com / filogic / atf / 3789104c8bdd134e91b57f599537cc39103b9521 / . / fdts / stm32mp131.dtsi
blob: dff1b33d82345500b5c9394c193392f2f2d514b5 [file] [log] [blame]
Yann Gautiercd736192020-02-25 15:14:52 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/clock/stm32mp13-clks.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/reset/stm32mp13-resets.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 device_type = "cpu";
21 reg = <0>;
22 clocks = <&rcc CK_MPU>;
23 clock-names = "cpu";
24 nvmem-cells = <&part_number_otp>;
25 nvmem-cell-names = "part_number";
26 };
27 };
28
29 nvmem_layout: nvmem_layout@0 {
30 compatible = "st,stm32-nvmem-layout";
31
32 nvmem-cells = <&cfg0_otp>,
33 <&part_number_otp>,
34 <&monotonic_otp>,
35 <&nand_otp>,
36 <&nand2_otp>,
37 <&uid_otp>,
38 <&hw2_otp>;
39
40 nvmem-cell-names = "cfg0_otp",
41 "part_number_otp",
42 "monotonic_otp",
43 "nand_otp",
44 "nand2_otp",
45 "uid_otp",
46 "hw2_otp";
47 };
48
49 clocks {
50 clk_csi: clk-csi {
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-frequency = <4000000>;
54 };
55
56 clk_hse: clk-hse {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
60 };
61
62 clk_hsi: clk-hsi {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <64000000>;
66 };
67
68 clk_lse: clk-lse {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <32768>;
72 };
73
74 clk_lsi: clk-lsi {
75 #clock-cells = <0>;
76 compatible = "fixed-clock";
77 clock-frequency = <32000>;
78 };
79 };
80
81 intc: interrupt-controller@a0021000 {
82 compatible = "arm,cortex-a7-gic";
83 #interrupt-cells = <3>;
84 interrupt-controller;
85 reg = <0xa0021000 0x1000>,
86 <0xa0022000 0x2000>;
87 };
88
89 psci {
90 compatible = "arm,psci-1.0";
91 method = "smc";
92 };
93
94 soc {
95 compatible = "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 interrupt-parent = <&intc>;
99 ranges;
100
101 usart3: serial@4000f000 {
102 compatible = "st,stm32h7-uart";
103 reg = <0x4000f000 0x400>;
104 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
105 clocks = <&rcc USART3_K>;
106 resets = <&rcc USART3_R>;
107 status = "disabled";
108 };
109
110 uart4: serial@40010000 {
111 compatible = "st,stm32h7-uart";
112 reg = <0x40010000 0x400>;
113 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&rcc UART4_K>;
115 resets = <&rcc UART4_R>;
116 status = "disabled";
117 };
118
119 uart5: serial@40011000 {
120 compatible = "st,stm32h7-uart";
121 reg = <0x40011000 0x400>;
122 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&rcc UART5_K>;
124 resets = <&rcc UART5_R>;
125 status = "disabled";
126 };
127
128 uart7: serial@40018000 {
129 compatible = "st,stm32h7-uart";
130 reg = <0x40018000 0x400>;
131 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&rcc UART7_K>;
133 resets = <&rcc UART7_R>;
134 status = "disabled";
135 };
136
137 uart8: serial@40019000 {
138 compatible = "st,stm32h7-uart";
139 reg = <0x40019000 0x400>;
140 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&rcc UART8_K>;
142 resets = <&rcc UART8_R>;
143 status = "disabled";
144 };
145
146 usart6: serial@44003000 {
147 compatible = "st,stm32h7-uart";
148 reg = <0x44003000 0x400>;
149 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&rcc USART6_K>;
151 resets = <&rcc USART6_R>;
152 status = "disabled";
153 };
154
155 usbotg_hs: usb-otg@49000000 {
156 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
157 reg = <0x49000000 0x40000>;
158 clocks = <&rcc USBO_K>;
159 clock-names = "otg";
160 resets = <&rcc USBO_R>;
161 reset-names = "dwc2";
162 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
163 g-rx-fifo-size = <512>;
164 g-np-tx-fifo-size = <32>;
165 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
166 dr_mode = "otg";
167 usb33d-supply = <&usb33>;
168 status = "disabled";
169 };
170
171 usart1: serial@4c000000 {
172 compatible = "st,stm32h7-uart";
173 reg = <0x4c000000 0x400>;
174 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&rcc USART1_K>;
176 resets = <&rcc USART1_R>;
177 status = "disabled";
178 };
179
180 usart2: serial@4c001000 {
181 compatible = "st,stm32h7-uart";
182 reg = <0x4c001000 0x400>;
183 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&rcc USART2_K>;
185 resets = <&rcc USART2_R>;
186 status = "disabled";
187 };
188
189 i2c3: i2c@4c004000 {
190 compatible = "st,stm32mp13-i2c";
191 reg = <0x4c004000 0x400>;
192 interrupt-names = "event", "error";
193 interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>,
194 <&intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&rcc I2C3_K>;
196 resets = <&rcc I2C3_R>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 st,syscfg-fmp = <&syscfg 0x4 0x4>;
200 i2c-analog-filter;
201 status = "disabled";
202 };
203
204 i2c4: i2c@4c005000 {
205 compatible = "st,stm32mp13-i2c";
206 reg = <0x4c005000 0x400>;
207 interrupt-names = "event", "error";
208 interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
209 <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&rcc I2C4_K>;
211 resets = <&rcc I2C4_R>;
212 #address-cells = <1>;
213 #size-cells = <0>;
214 st,syscfg-fmp = <&syscfg 0x4 0x8>;
215 i2c-analog-filter;
216 status = "disabled";
217 };
218
219 i2c5: i2c@4c006000 {
220 compatible = "st,stm32mp13-i2c";
221 reg = <0x4c006000 0x400>;
222 interrupt-names = "event", "error";
223 interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>,
224 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&rcc I2C5_K>;
226 resets = <&rcc I2C5_R>;
227 #address-cells = <1>;
228 #size-cells = <0>;
229 st,syscfg-fmp = <&syscfg 0x4 0x10>;
230 i2c-analog-filter;
231 status = "disabled";
232 };
233
234 rcc: rcc@50000000 {
235 compatible = "st,stm32mp13-rcc", "syscon";
236 reg = <0x50000000 0x1000>;
237 #address-cells = <1>;
238 #size-cells = <0>;
239 #clock-cells = <1>;
240 #reset-cells = <1>;
241 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
242 secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
243 secure-interrupt-names = "wakeup";
244 };
245
246 pwr_regulators: pwr@50001000 {
247 compatible = "st,stm32mp1,pwr-reg";
248 reg = <0x50001000 0x10>;
249
250 reg11: reg11 {
251 regulator-name = "reg11";
252 regulator-min-microvolt = <1100000>;
253 regulator-max-microvolt = <1100000>;
254 };
255
256 reg18: reg18 {
257 regulator-name = "reg18";
258 regulator-min-microvolt = <1800000>;
259 regulator-max-microvolt = <1800000>;
260 };
261
262 usb33: usb33 {
263 regulator-name = "usb33";
264 regulator-min-microvolt = <3300000>;
265 regulator-max-microvolt = <3300000>;
266 };
267 };
268
269 exti: interrupt-controller@5000d000 {
270 compatible = "st,stm32mp13-exti", "syscon";
271 interrupt-controller;
272 #interrupt-cells = <2>;
273 reg = <0x5000d000 0x400>;
274 };
275
276 syscfg: syscon@50020000 {
277 compatible = "st,stm32mp157-syscfg", "syscon";
278 reg = <0x50020000 0x400>;
279 clocks = <&rcc SYSCFG>;
280 };
281
282 vrefbuf: vrefbuf@50025000 {
283 compatible = "st,stm32-vrefbuf";
284 reg = <0x50025000 0x8>;
285 regulator-min-microvolt = <1500000>;
286 regulator-max-microvolt = <2500000>;
287 clocks = <&rcc VREF>;
288 status = "disabled";
289 };
290
291 hash: hash@54003000 {
292 compatible = "st,stm32mp13-hash";
293 reg = <0x54003000 0x400>;
294 clocks = <&rcc HASH1>;
295 resets = <&rcc HASH1_R>;
296 status = "disabled";
297 };
298
299 rng: rng@54004000 {
300 compatible = "st,stm32mp13-rng";
301 reg = <0x54004000 0x400>;
302 clocks = <&rcc RNG1_K>;
303 resets = <&rcc RNG1_R>;
304 status = "disabled";
305 };
306
307 fmc: memory-controller@58002000 {
308 #address-cells = <2>;
309 #size-cells = <1>;
310 compatible = "st,stm32mp1-fmc2-ebi";
311 reg = <0x58002000 0x1000>;
312 clocks = <&rcc FMC_K>;
313 resets = <&rcc FMC_R>;
314 status = "disabled";
315
316 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
317 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
318 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
319 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
320 <4 0 0x80000000 0x10000000>; /* NAND */
321
322 nand-controller@4,0 {
323 #address-cells = <1>;
324 #size-cells = <0>;
325 compatible = "st,stm32mp1-fmc2-nfc";
326 reg = <4 0x00000000 0x1000>,
327 <4 0x08010000 0x1000>,
328 <4 0x08020000 0x1000>,
329 <4 0x01000000 0x1000>,
330 <4 0x09010000 0x1000>,
331 <4 0x09020000 0x1000>;
332 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
333 status = "disabled";
334 };
335 };
336
337 qspi: spi@58003000 {
338 compatible = "st,stm32f469-qspi";
339 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
340 reg-names = "qspi", "qspi_mm";
341 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&rcc QSPI_K>;
343 resets = <&rcc QSPI_R>;
344 status = "disabled";
345 };
346
347 sdmmc1: mmc@58005000 {
348 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
349 arm,primecell-periphid = <0x20253180>;
350 reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
351 clocks = <&rcc SDMMC1_K>;
352 clock-names = "apb_pclk";
353 resets = <&rcc SDMMC1_R>;
354 cap-sd-highspeed;
355 cap-mmc-highspeed;
356 max-frequency = <120000000>;
357 status = "disabled";
358 };
359
360 sdmmc2: mmc@58007000 {
361 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
362 arm,primecell-periphid = <0x20253180>;
363 reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
364 clocks = <&rcc SDMMC2_K>;
365 clock-names = "apb_pclk";
366 resets = <&rcc SDMMC2_R>;
367 cap-sd-highspeed;
368 cap-mmc-highspeed;
369 max-frequency = <120000000>;
370 status = "disabled";
371 };
372
373 crc1: crc@58009000 {
374 compatible = "st,stm32f7-crc";
375 reg = <0x58009000 0x400>;
376 clocks = <&rcc CRC1>;
377 };
378
379 usbh_ohci: usbh-ohci@5800c000 {
380 compatible = "generic-ohci";
381 reg = <0x5800c000 0x1000>;
382 clocks = <&rcc USBH>;
383 resets = <&rcc USBH_R>;
384 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
385 status = "disabled";
386 };
387
388 usbh_ehci: usbh-ehci@5800d000 {
389 compatible = "generic-ehci";
390 reg = <0x5800d000 0x1000>;
391 clocks = <&rcc USBH>;
392 resets = <&rcc USBH_R>;
393 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
394 companion = <&usbh_ohci>;
395 status = "disabled";
396 };
397
398 iwdg2: watchdog@5a002000 {
399 compatible = "st,stm32mp1-iwdg";
400 reg = <0x5a002000 0x400>;
401 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
402 clock-names = "pclk", "lsi";
403 status = "disabled";
404 };
405
Nicolas Le Bayon01087912021-01-12 18:18:27 +0100[diff] [blame]406 ddr: ddr@5a003000{
407 compatible = "st,stm32mp13-ddr";
408 reg = <0x5a003000 0x550>, <0x5a004000 0x234>;
409 clocks = <&rcc AXIDCG>,
410 <&rcc DDRC1>,
411 <&rcc DDRPHYC>,
412 <&rcc DDRCAPB>,
413 <&rcc DDRPHYCAPB>;
414 clock-names = "axidcg",
415 "ddrc1",
416 "ddrphyc",
417 "ddrcapb",
418 "ddrphycapb";
419 };
420
Yann Gautiercd736192020-02-25 15:14:52 +0100[diff] [blame]421 usbphyc: usbphyc@5a006000 {
422 #address-cells = <1>;
423 #size-cells = <0>;
424 #clock-cells = <0>;
425 compatible = "st,stm32mp1-usbphyc";
426 reg = <0x5a006000 0x1000>;
427 clocks = <&rcc USBPHY_K>;
428 resets = <&rcc USBPHY_R>;
429 vdda1v1-supply = <&reg11>;
430 vdda1v8-supply = <&reg18>;
431 status = "disabled";
432
433 usbphyc_port0: usb-phy@0 {
434 #phy-cells = <0>;
435 reg = <0>;
436 };
437
438 usbphyc_port1: usb-phy@1 {
439 #phy-cells = <1>;
440 reg = <1>;
441 };
442 };
443
444 iwdg1: watchdog@5c003000 {
445 compatible = "st,stm32mp1-iwdg";
446 reg = <0x5c003000 0x400>;
447 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
449 clock-names = "pclk", "lsi";
450 status = "disabled";
451 };
452
453 bsec: efuse@5c005000 {
454 compatible = "st,stm32mp15-bsec";
455 reg = <0x5c005000 0x400>;
456 #address-cells = <1>;
457 #size-cells = <1>;
458
459 cfg0_otp: cfg0_otp@0 {
460 reg = <0x0 0x2>;
461 };
462 part_number_otp: part_number_otp@4 {
463 reg = <0x4 0x2>;
464 };
465 monotonic_otp: monotonic_otp@10 {
466 reg = <0x10 0x4>;
467 };
468 nand_otp: cfg9_otp@24 {
469 reg = <0x24 0x4>;
470 };
471 nand2_otp: cfg10_otp@28 {
472 reg = <0x28 0x4>;
473 };
474 uid_otp: uid_otp@34 {
475 reg = <0x34 0xc>;
476 };
477 hw2_otp: hw2_otp@48 {
478 reg = <0x48 0x4>;
479 };
480 ts_cal1: calib@5c {
481 reg = <0x5c 0x2>;
482 };
483 ts_cal2: calib@5e {
484 reg = <0x5e 0x2>;
485 };
486 pkh_otp: pkh_otp@60 {
487 reg = <0x60 0x20>;
488 };
489 mac_addr: mac_addr@e4 {
490 reg = <0xe4 0xc>;
491 st,non-secure-otp;
492 };
493 };
494
495 tamp: tamp@5c00a000 {
496 reg = <0x5c00a000 0x400>;
497 };
498
499 /*
500 * Break node order to solve dependency probe issue between
501 * pinctrl and exti.
502 */
503 pinctrl: pin-controller@50002000 {
504 #address-cells = <1>;
505 #size-cells = <1>;
506 compatible = "st,stm32mp135-pinctrl";
507 ranges = <0 0x50002000 0x8400>;
508 interrupt-parent = <&exti>;
509 st,syscfg = <&exti 0x60 0xff>;
510 pins-are-numbered;
511
512 gpioa: gpio@50002000 {
513 gpio-controller;
514 #gpio-cells = <2>;
515 interrupt-controller;
516 #interrupt-cells = <2>;
517 reg = <0x0 0x400>;
518 clocks = <&rcc GPIOA>;
519 st,bank-name = "GPIOA";
520 ngpios = <16>;
521 gpio-ranges = <&pinctrl 0 0 16>;
522 };
523
524 gpiob: gpio@50003000 {
525 gpio-controller;
526 #gpio-cells = <2>;
527 interrupt-controller;
528 #interrupt-cells = <2>;
529 reg = <0x1000 0x400>;
530 clocks = <&rcc GPIOB>;
531 st,bank-name = "GPIOB";
532 ngpios = <16>;
533 gpio-ranges = <&pinctrl 0 16 16>;
534 };
535
536 gpioc: gpio@50004000 {
537 gpio-controller;
538 #gpio-cells = <2>;
539 interrupt-controller;
540 #interrupt-cells = <2>;
541 reg = <0x2000 0x400>;
542 clocks = <&rcc GPIOC>;
543 st,bank-name = "GPIOC";
544 ngpios = <16>;
545 gpio-ranges = <&pinctrl 0 32 16>;
546 };
547
548 gpiod: gpio@50005000 {
549 gpio-controller;
550 #gpio-cells = <2>;
551 interrupt-controller;
552 #interrupt-cells = <2>;
553 reg = <0x3000 0x400>;
554 clocks = <&rcc GPIOD>;
555 st,bank-name = "GPIOD";
556 ngpios = <16>;
557 gpio-ranges = <&pinctrl 0 48 16>;
558 };
559
560 gpioe: gpio@50006000 {
561 gpio-controller;
562 #gpio-cells = <2>;
563 interrupt-controller;
564 #interrupt-cells = <2>;
565 reg = <0x4000 0x400>;
566 clocks = <&rcc GPIOE>;
567 st,bank-name = "GPIOE";
568 ngpios = <16>;
569 gpio-ranges = <&pinctrl 0 64 16>;
570 };
571
572 gpiof: gpio@50007000 {
573 gpio-controller;
574 #gpio-cells = <2>;
575 interrupt-controller;
576 #interrupt-cells = <2>;
577 reg = <0x5000 0x400>;
578 clocks = <&rcc GPIOF>;
579 st,bank-name = "GPIOF";
580 ngpios = <16>;
581 gpio-ranges = <&pinctrl 0 80 16>;
582 };
583
584 gpiog: gpio@50008000 {
585 gpio-controller;
586 #gpio-cells = <2>;
587 interrupt-controller;
588 #interrupt-cells = <2>;
589 reg = <0x6000 0x400>;
590 clocks = <&rcc GPIOG>;
591 st,bank-name = "GPIOG";
592 ngpios = <16>;
593 gpio-ranges = <&pinctrl 0 96 16>;
594 };
595
596 gpioh: gpio@50009000 {
597 gpio-controller;
598 #gpio-cells = <2>;
599 interrupt-controller;
600 #interrupt-cells = <2>;
601 reg = <0x7000 0x400>;
602 clocks = <&rcc GPIOH>;
603 st,bank-name = "GPIOH";
604 ngpios = <15>;
605 gpio-ranges = <&pinctrl 0 112 15>;
606 };
607
608 gpioi: gpio@5000a000 {
609 gpio-controller;
610 #gpio-cells = <2>;
611 interrupt-controller;
612 #interrupt-cells = <2>;
613 reg = <0x8000 0x400>;
614 clocks = <&rcc GPIOI>;
615 st,bank-name = "GPIOI";
616 ngpios = <8>;
617 gpio-ranges = <&pinctrl 0 128 8>;
618 };
619 };
620 };
621};