Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <stdio.h> |
| 32 | #include <string.h> |
| 33 | #include <assert.h> |
Achin Gupta | 0a9f747 | 2014-02-09 17:48:12 +0000 | [diff] [blame] | 34 | #include <debug.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 35 | #include <arch_helpers.h> |
| 36 | #include <console.h> |
| 37 | #include <platform.h> |
| 38 | #include <psci.h> |
| 39 | #include <psci_private.h> |
| 40 | |
| 41 | typedef int (*afflvl_off_handler)(unsigned long, aff_map_node *); |
| 42 | |
| 43 | /******************************************************************************* |
| 44 | * The next three functions implement a handler for each supported affinity |
| 45 | * level which is called when that affinity level is turned off. |
| 46 | ******************************************************************************/ |
| 47 | static int psci_afflvl0_off(unsigned long mpidr, aff_map_node *cpu_node) |
| 48 | { |
| 49 | unsigned int index, plat_state; |
| 50 | int rc = PSCI_E_SUCCESS; |
| 51 | unsigned long sctlr = read_sctlr(); |
| 52 | |
| 53 | assert(cpu_node->level == MPIDR_AFFLVL0); |
| 54 | |
Achin Gupta | 75f7367 | 2013-12-05 16:33:10 +0000 | [diff] [blame] | 55 | /* State management: mark this cpu as turned off */ |
| 56 | psci_set_state(cpu_node, PSCI_STATE_OFF); |
| 57 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 58 | /* |
| 59 | * Generic management: Get the index for clearing any |
| 60 | * lingering re-entry information |
| 61 | */ |
| 62 | index = cpu_node->data; |
| 63 | memset(&psci_ns_entry_info[index], 0, sizeof(psci_ns_entry_info[index])); |
| 64 | |
| 65 | /* |
| 66 | * Arch. management. Perform the necessary steps to flush all |
| 67 | * cpu caches. |
| 68 | * |
| 69 | * TODO: This power down sequence varies across cpus so it needs to be |
| 70 | * abstracted out on the basis of the MIDR like in cpu_reset_handler(). |
| 71 | * Do the bare minimal for the time being. Fix this before porting to |
| 72 | * Cortex models. |
| 73 | */ |
| 74 | sctlr &= ~SCTLR_C_BIT; |
| 75 | write_sctlr(sctlr); |
| 76 | |
| 77 | /* |
| 78 | * CAUTION: This flush to the level of unification makes an assumption |
| 79 | * about the cache hierarchy at affinity level 0 (cpu) in the platform. |
| 80 | * Ideally the platform should tell psci which levels to flush to exit |
| 81 | * coherency. |
| 82 | */ |
| 83 | dcsw_op_louis(DCCISW); |
| 84 | |
| 85 | /* |
| 86 | * Plat. management: Perform platform specific actions to turn this |
| 87 | * cpu off e.g. exit cpu coherency, program the power controller etc. |
| 88 | */ |
| 89 | if (psci_plat_pm_ops->affinst_off) { |
| 90 | |
| 91 | /* Get the current physical state of this cpu */ |
Achin Gupta | 75f7367 | 2013-12-05 16:33:10 +0000 | [diff] [blame] | 92 | plat_state = psci_get_phys_state(cpu_node); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 93 | rc = psci_plat_pm_ops->affinst_off(mpidr, |
| 94 | cpu_node->level, |
| 95 | plat_state); |
| 96 | } |
| 97 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 98 | return rc; |
| 99 | } |
| 100 | |
| 101 | static int psci_afflvl1_off(unsigned long mpidr, aff_map_node *cluster_node) |
| 102 | { |
| 103 | int rc = PSCI_E_SUCCESS; |
| 104 | unsigned int plat_state; |
| 105 | |
| 106 | /* Sanity check the cluster level */ |
| 107 | assert(cluster_node->level == MPIDR_AFFLVL1); |
| 108 | |
Achin Gupta | 75f7367 | 2013-12-05 16:33:10 +0000 | [diff] [blame] | 109 | /* State management: Decrement the cluster reference count */ |
| 110 | psci_set_state(cluster_node, PSCI_STATE_OFF); |
| 111 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 112 | /* |
| 113 | * Keep the physical state of this cluster handy to decide |
| 114 | * what action needs to be taken |
| 115 | */ |
Achin Gupta | 75f7367 | 2013-12-05 16:33:10 +0000 | [diff] [blame] | 116 | plat_state = psci_get_phys_state(cluster_node); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 117 | |
| 118 | /* |
| 119 | * Arch. Management. Flush all levels of caches to PoC if |
| 120 | * the cluster is to be shutdown |
| 121 | */ |
| 122 | if (plat_state == PSCI_STATE_OFF) |
| 123 | dcsw_op_all(DCCISW); |
| 124 | |
| 125 | /* |
Achin Gupta | 3140a9e | 2013-12-02 16:23:12 +0000 | [diff] [blame] | 126 | * Plat. Management. Allow the platform to do its cluster |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 127 | * specific bookeeping e.g. turn off interconnect coherency, |
| 128 | * program the power controller etc. |
| 129 | */ |
| 130 | if (psci_plat_pm_ops->affinst_off) |
| 131 | rc = psci_plat_pm_ops->affinst_off(mpidr, |
| 132 | cluster_node->level, |
| 133 | plat_state); |
| 134 | |
| 135 | return rc; |
| 136 | } |
| 137 | |
| 138 | static int psci_afflvl2_off(unsigned long mpidr, aff_map_node *system_node) |
| 139 | { |
| 140 | int rc = PSCI_E_SUCCESS; |
| 141 | unsigned int plat_state; |
| 142 | |
| 143 | /* Cannot go beyond this level */ |
| 144 | assert(system_node->level == MPIDR_AFFLVL2); |
| 145 | |
Achin Gupta | 75f7367 | 2013-12-05 16:33:10 +0000 | [diff] [blame] | 146 | /* State management: Decrement the system reference count */ |
| 147 | psci_set_state(system_node, PSCI_STATE_OFF); |
| 148 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 149 | /* |
| 150 | * Keep the physical state of the system handy to decide what |
| 151 | * action needs to be taken |
| 152 | */ |
Achin Gupta | 75f7367 | 2013-12-05 16:33:10 +0000 | [diff] [blame] | 153 | plat_state = psci_get_phys_state(system_node); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 154 | |
| 155 | /* No arch. and generic bookeeping to do here currently */ |
| 156 | |
| 157 | /* |
Achin Gupta | 3140a9e | 2013-12-02 16:23:12 +0000 | [diff] [blame] | 158 | * Plat. Management : Allow the platform to do its bookeeping |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 159 | * at this affinity level |
| 160 | */ |
| 161 | if (psci_plat_pm_ops->affinst_off) |
| 162 | rc = psci_plat_pm_ops->affinst_off(mpidr, |
| 163 | system_node->level, |
| 164 | plat_state); |
| 165 | return rc; |
| 166 | } |
| 167 | |
| 168 | static const afflvl_off_handler psci_afflvl_off_handlers[] = { |
| 169 | psci_afflvl0_off, |
| 170 | psci_afflvl1_off, |
| 171 | psci_afflvl2_off, |
| 172 | }; |
| 173 | |
| 174 | /******************************************************************************* |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 175 | * This function takes an array of pointers to affinity instance nodes in the |
| 176 | * topology tree and calls the off handler for the corresponding affinity |
| 177 | * levels |
| 178 | ******************************************************************************/ |
| 179 | static int psci_call_off_handlers(mpidr_aff_map_nodes mpidr_nodes, |
| 180 | int start_afflvl, |
| 181 | int end_afflvl, |
| 182 | unsigned long mpidr) |
| 183 | { |
| 184 | int rc = PSCI_E_INVALID_PARAMS, level; |
| 185 | aff_map_node *node; |
| 186 | |
| 187 | for (level = start_afflvl; level <= end_afflvl; level++) { |
| 188 | node = mpidr_nodes[level]; |
| 189 | if (node == NULL) |
| 190 | continue; |
| 191 | |
| 192 | /* |
| 193 | * TODO: In case of an error should there be a way |
| 194 | * of restoring what we might have torn down at |
| 195 | * lower affinity levels. |
| 196 | */ |
| 197 | rc = psci_afflvl_off_handlers[level](mpidr, node); |
| 198 | if (rc != PSCI_E_SUCCESS) |
| 199 | break; |
| 200 | } |
| 201 | |
| 202 | return rc; |
| 203 | } |
| 204 | |
| 205 | /******************************************************************************* |
| 206 | * Top level handler which is called when a cpu wants to power itself down. |
| 207 | * It's assumed that along with turning the cpu off, higher affinity levels will |
| 208 | * be turned off as far as possible. It traverses through all the affinity |
| 209 | * levels performing generic, architectural, platform setup and state management |
| 210 | * e.g. for a cluster that's to be powered off, it will call the platform |
| 211 | * specific code which will disable coherency at the interconnect level if the |
| 212 | * cpu is the last in the cluster. For a cpu it could mean programming the power |
| 213 | * the power controller etc. |
| 214 | * |
| 215 | * The state of all the relevant affinity levels is changed prior to calling the |
| 216 | * affinity level specific handlers as their actions would depend upon the state |
| 217 | * the affinity level is about to enter. |
| 218 | * |
| 219 | * The affinity level specific handlers are called in ascending order i.e. from |
| 220 | * the lowest to the highest affinity level implemented by the platform because |
| 221 | * to turn off affinity level X it is neccesary to turn off affinity level X - 1 |
| 222 | * first. |
| 223 | * |
| 224 | * CAUTION: This function is called with coherent stacks so that coherency can |
| 225 | * be turned off and caches can be flushed safely. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 226 | ******************************************************************************/ |
| 227 | int psci_afflvl_off(unsigned long mpidr, |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 228 | int start_afflvl, |
| 229 | int end_afflvl) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 230 | { |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 231 | int rc = PSCI_E_SUCCESS; |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 232 | mpidr_aff_map_nodes mpidr_nodes; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 233 | |
| 234 | mpidr &= MPIDR_AFFINITY_MASK;; |
| 235 | |
| 236 | /* |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 237 | * Collect the pointers to the nodes in the topology tree for |
| 238 | * each affinity instance in the mpidr. If this function does |
| 239 | * not return successfully then either the mpidr or the affinity |
| 240 | * levels are incorrect. In either case, we cannot return back |
| 241 | * to the caller as it would not know what to do. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 242 | */ |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 243 | rc = psci_get_aff_map_nodes(mpidr, |
| 244 | start_afflvl, |
| 245 | end_afflvl, |
| 246 | mpidr_nodes); |
| 247 | assert (rc == PSCI_E_SUCCESS); |
| 248 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 249 | /* |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 250 | * This function acquires the lock corresponding to each affinity |
| 251 | * level so that by the time all locks are taken, the system topology |
| 252 | * is snapshot and state management can be done safely. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 253 | */ |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 254 | psci_acquire_afflvl_locks(mpidr, |
| 255 | start_afflvl, |
| 256 | end_afflvl, |
| 257 | mpidr_nodes); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 258 | |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 259 | /* Perform generic, architecture and platform specific handling */ |
| 260 | rc = psci_call_off_handlers(mpidr_nodes, |
| 261 | start_afflvl, |
| 262 | end_afflvl, |
| 263 | mpidr); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 264 | |
| 265 | /* |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 266 | * Release the locks corresponding to each affinity level in the |
| 267 | * reverse order to which they were acquired. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 268 | */ |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 269 | psci_release_afflvl_locks(mpidr, |
| 270 | start_afflvl, |
| 271 | end_afflvl, |
| 272 | mpidr_nodes); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 273 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 274 | return rc; |
| 275 | } |