johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 1 | /* |
Sona Mathew | ed5e976 | 2023-06-19 21:30:45 -0500 | [diff] [blame] | 2 | * Copyright (c) 2021-2023, Arm Limited. All rights reserved. |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 10 | #include <cortex_x3.h> |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 13 | #include "wa_cve_2022_23960_bhb_vector.S" |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 14 | |
| 15 | /* Hardware handled coherency */ |
| 16 | #if HW_ASSISTED_COHERENCY == 0 |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 17 | #error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 18 | #endif |
| 19 | |
| 20 | /* 64-bit only core */ |
| 21 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 22 | #error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 23 | #endif |
| 24 | |
Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 25 | #if WORKAROUND_CVE_2022_23960 |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 26 | wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 |
Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 27 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 28 | |
Sona Mathew | 35c7d39 | 2023-10-03 17:09:09 -0500 | [diff] [blame] | 29 | workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301 |
| 30 | sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \ |
| 31 | CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH |
| 32 | workaround_reset_end cortex_x3, ERRATUM(2070301) |
| 33 | |
| 34 | check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2) |
| 35 | |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 36 | workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 |
Sona Mathew | 45c1524 | 2023-06-20 00:16:44 -0500 | [diff] [blame] | 37 | sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 38 | workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB |
Boyan Karatotev | 6559dbd | 2022-10-03 14:18:28 +0100 | [diff] [blame] | 39 | |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 40 | check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0) |
Harrison Mutai | 82dd5ac | 2022-11-11 14:09:55 +0000 | [diff] [blame] | 41 | |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 42 | workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812 |
Harrison Mutai | 82dd5ac | 2022-11-11 14:09:55 +0000 | [diff] [blame] | 43 | /* Disable retention control for WFI and WFE. */ |
| 44 | mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 |
| 45 | bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 |
| 46 | bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 |
| 47 | msr CORTEX_X3_CPUPWRCTLR_EL1, x0 |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 48 | workaround_reset_end cortex_x3, ERRATUM(2615812) |
Harrison Mutai | 82dd5ac | 2022-11-11 14:09:55 +0000 | [diff] [blame] | 49 | |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 50 | check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1) |
Harrison Mutai | 82dd5ac | 2022-11-11 14:09:55 +0000 | [diff] [blame] | 51 | |
Sona Mathew | 9516858 | 2023-09-05 14:10:03 -0500 | [diff] [blame] | 52 | workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421 |
| 53 | /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ |
| 54 | sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55 |
| 55 | sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56 |
| 56 | workaround_reset_end cortex_x3, ERRATUM(2742421) |
| 57 | |
| 58 | check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1) |
| 59 | |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 60 | workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 61 | #if IMAGE_BL31 |
Sona Mathew | 45c1524 | 2023-06-20 00:16:44 -0500 | [diff] [blame] | 62 | override_vector_table wa_cve_vbar_cortex_x3 |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 63 | #endif /* IMAGE_BL31 */ |
| 64 | workaround_reset_end cortex_x3, CVE(2022, 23960) |
| 65 | |
| 66 | check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
Sona Mathew | ed5e976 | 2023-06-19 21:30:45 -0500 | [diff] [blame] | 67 | |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 68 | cpu_reset_func_start cortex_x3 |
Sona Mathew | ed5e976 | 2023-06-19 21:30:45 -0500 | [diff] [blame] | 69 | /* Disable speculative loads */ |
| 70 | msr SSBS, xzr |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 71 | cpu_reset_func_end cortex_x3 |
Sona Mathew | ed5e976 | 2023-06-19 21:30:45 -0500 | [diff] [blame] | 72 | |
| 73 | /* ---------------------------------------------------- |
| 74 | * HW will do the cache maintenance while powering down |
| 75 | * ---------------------------------------------------- |
| 76 | */ |
| 77 | func cortex_x3_core_pwr_dwn |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 78 | apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 |
Sona Mathew | ed5e976 | 2023-06-19 21:30:45 -0500 | [diff] [blame] | 79 | /* --------------------------------------------------- |
| 80 | * Enable CPU power down bit in power control register |
| 81 | * --------------------------------------------------- |
| 82 | */ |
Sona Mathew | 45c1524 | 2023-06-20 00:16:44 -0500 | [diff] [blame] | 83 | sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
Sona Mathew | ed5e976 | 2023-06-19 21:30:45 -0500 | [diff] [blame] | 84 | isb |
| 85 | ret |
| 86 | endfunc cortex_x3_core_pwr_dwn |
| 87 | |
Sona Mathew | d928f48 | 2023-06-19 22:15:51 -0500 | [diff] [blame] | 88 | errata_report_shim cortex_x3 |
Bipin Ravi | 32464ba | 2022-05-06 16:02:30 -0500 | [diff] [blame] | 89 | |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 90 | /* --------------------------------------------- |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 91 | * This function provides Cortex-X3- |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 92 | * specific register information for crash |
| 93 | * reporting. It needs to return with x6 |
| 94 | * pointing to a list of register names in ascii |
| 95 | * and x8 - x15 having values of registers to be |
| 96 | * reported. |
| 97 | * --------------------------------------------- |
| 98 | */ |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 99 | .section .rodata.cortex_x3_regs, "aS" |
| 100 | cortex_x3_regs: /* The ascii list of register names to be reported */ |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 101 | .asciz "cpuectlr_el1", "" |
| 102 | |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 103 | func cortex_x3_cpu_reg_dump |
| 104 | adr x6, cortex_x3_regs |
| 105 | mrs x8, CORTEX_X3_CPUECTLR_EL1 |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 106 | ret |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 107 | endfunc cortex_x3_cpu_reg_dump |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 108 | |
Boyan Karatotev | bdf953c | 2022-10-25 11:29:04 +0100 | [diff] [blame] | 109 | declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \ |
| 110 | cortex_x3_reset_func, \ |
| 111 | cortex_x3_core_pwr_dwn |