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git01.mediatek.com / filogic / atf / 36f029bd6d028fc6800c1afe0ddc05a880d0853c / . / fdts / rd1ae.dts
blob: 3060b5a72a84528e71eaa493a9ab7668d092166f [file] [log] [blame]
Divin Raj70a044f2024-04-04 14:00:36 +0100[diff] [blame]1/*
2 * Copyright (c) 2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12 model = "RD-1 AE";
13 compatible = "arm,rd1ae", "arm,neoverse";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 chosen {
19 stdout-path = &soc_serial0;
20 };
21
22 cpus {
23 #address-cells = <2>;
24 #size-cells = <0>;
25
26 cpu0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,neoverse-v3";
29 reg = <0x0 0x0>;
30 enable-method = "psci";
31 i-cache-size = <0x10000>;
32 i-cache-line-size = <0x40>;
33 i-cache-sets = <0x100>;
34 d-cache-size = <0x10000>;
35 d-cache-line-size = <0x40>;
36 d-cache-sets = <0x100>;
37 };
38 cpu1: cpu@10000 {
39 device_type = "cpu";
40 compatible = "arm,neoverse-v3";
41 reg = <0x0 0x10000>;
42 enable-method = "psci";
43 i-cache-size = <0x10000>;
44 i-cache-line-size = <0x40>;
45 i-cache-sets = <0x100>;
46 d-cache-size = <0x10000>;
47 d-cache-line-size = <0x40>;
48 d-cache-sets = <0x100>;
49 };
50 cpu2: cpu@20000 {
51 device_type = "cpu";
52 compatible = "arm,neoverse-v3";
53 reg = <0x0 0x20000>;
54 enable-method = "psci";
55 i-cache-size = <0x10000>;
56 i-cache-line-size = <0x40>;
57 i-cache-sets = <0x100>;
58 d-cache-size = <0x10000>;
59 d-cache-line-size = <0x40>;
60 d-cache-sets = <0x100>;
61 };
62 cpu3: cpu@30000 {
63 device_type = "cpu";
64 compatible = "arm,neoverse-v3";
65 reg = <0x0 0x30000>;
66 enable-method = "psci";
67 i-cache-size = <0x10000>;
68 i-cache-line-size = <0x40>;
69 i-cache-sets = <0x100>;
70 d-cache-size = <0x10000>;
71 d-cache-line-size = <0x40>;
72 d-cache-sets = <0x100>;
73 };
74 cpu4: cpu@40000 {
75 device_type = "cpu";
76 compatible = "arm,neoverse-v3";
77 reg = <0x0 0x40000>;
78 enable-method = "psci";
79 i-cache-size = <0x10000>;
80 i-cache-line-size = <0x40>;
81 i-cache-sets = <0x100>;
82 d-cache-size = <0x10000>;
83 d-cache-line-size = <0x40>;
84 d-cache-sets = <0x100>;
85 };
86 cpu5: cpu@50000 {
87 device_type = "cpu";
88 compatible = "arm,neoverse-v3";
89 reg = <0x0 0x50000>;
90 enable-method = "psci";
91 i-cache-size = <0x10000>;
92 i-cache-line-size = <0x40>;
93 i-cache-sets = <0x100>;
94 d-cache-size = <0x10000>;
95 d-cache-line-size = <0x40>;
96 d-cache-sets = <0x100>;
97 };
98 cpu6: cpu@60000 {
99 device_type = "cpu";
100 compatible = "arm,neoverse-v3";
101 reg = <0x0 0x60000>;
102 enable-method = "psci";
103 i-cache-size = <0x10000>;
104 i-cache-line-size = <0x40>;
105 i-cache-sets = <0x100>;
106 d-cache-size = <0x10000>;
107 d-cache-line-size = <0x40>;
108 d-cache-sets = <0x100>;
109 };
110 cpu7: cpu@70000 {
111 device_type = "cpu";
112 compatible = "arm,neoverse-v3";
113 reg = <0x0 0x70000>;
114 enable-method = "psci";
115 i-cache-size = <0x10000>;
116 i-cache-line-size = <0x40>;
117 i-cache-sets = <0x100>;
118 d-cache-size = <0x10000>;
119 d-cache-line-size = <0x40>;
120 d-cache-sets = <0x100>;
121 };
122 cpu8: cpu@80000 {
123 device_type = "cpu";
124 compatible = "arm,neoverse-v3";
125 reg = <0x0 0x80000>;
126 enable-method = "psci";
127 i-cache-size = <0x10000>;
128 i-cache-line-size = <0x40>;
129 i-cache-sets = <0x100>;
130 d-cache-size = <0x10000>;
131 d-cache-line-size = <0x40>;
132 d-cache-sets = <0x100>;
133 };
134 cpu9: cpu@90000 {
135 device_type = "cpu";
136 compatible = "arm,neoverse-v3";
137 reg = <0x0 0x90000>;
138 enable-method = "psci";
139 i-cache-size = <0x10000>;
140 i-cache-line-size = <0x40>;
141 i-cache-sets = <0x100>;
142 d-cache-size = <0x10000>;
143 d-cache-line-size = <0x40>;
144 d-cache-sets = <0x100>;
145 };
146 cpu10: cpu@a0000 {
147 device_type = "cpu";
148 compatible = "arm,neoverse-v3";
149 reg = <0x0 0xa0000>;
150 enable-method = "psci";
151 i-cache-size = <0x10000>;
152 i-cache-line-size = <0x40>;
153 i-cache-sets = <0x100>;
154 d-cache-size = <0x10000>;
155 d-cache-line-size = <0x40>;
156 d-cache-sets = <0x100>;
157 };
158 cpu11: cpu@b0000 {
159 device_type = "cpu";
160 compatible = "arm,neoverse-v3";
161 reg = <0x0 0xb0000>;
162 enable-method = "psci";
163 i-cache-size = <0x10000>;
164 i-cache-line-size = <0x40>;
165 i-cache-sets = <0x100>;
166 d-cache-size = <0x10000>;
167 d-cache-line-size = <0x40>;
168 d-cache-sets = <0x100>;
169 };
170 cpu12: cpu@c0000 {
171 device_type = "cpu";
172 compatible = "arm,neoverse-v3";
173 reg = <0x0 0xc0000>;
174 enable-method = "psci";
175 i-cache-size = <0x10000>;
176 i-cache-line-size = <0x40>;
177 i-cache-sets = <0x100>;
178 d-cache-size = <0x10000>;
179 d-cache-line-size = <0x40>;
180 d-cache-sets = <0x100>;
181 };
182 cpu13: cpu@d0000 {
183 device_type = "cpu";
184 compatible = "arm,neoverse-v3";
185 reg = <0x0 0xd0000>;
186 enable-method = "psci";
187 i-cache-size = <0x10000>;
188 i-cache-line-size = <0x40>;
189 i-cache-sets = <0x100>;
190 d-cache-size = <0x10000>;
191 d-cache-line-size = <0x40>;
192 d-cache-sets = <0x100>;
193 };
194 cpu14: cpu@e0000 {
195 device_type = "cpu";
196 compatible = "arm,neoverse-v3";
197 reg = <0x0 0xe0000>;
198 enable-method = "psci";
199 i-cache-size = <0x10000>;
200 i-cache-line-size = <0x40>;
201 i-cache-sets = <0x100>;
202 d-cache-size = <0x10000>;
203 d-cache-line-size = <0x40>;
204 d-cache-sets = <0x100>;
205 };
206 cpu15: cpu@f0000 {
207 device_type = "cpu";
208 compatible = "arm,neoverse-v3";
209 reg = <0x0 0xf0000>;
210 enable-method = "psci";
211 i-cache-size = <0x10000>;
212 i-cache-line-size = <0x40>;
213 i-cache-sets = <0x100>;
214 d-cache-size = <0x10000>;
215 d-cache-line-size = <0x40>;
216 d-cache-sets = <0x100>;
217 };
218 };
219
220 memory@80000000 {
221 device_type = "memory";
222 /*
223 * 0x7fc0 0000 - 0x7fff ffff : BL32
224 * 0x7fbf 0000 - 0x7fbf ffff : FFA_SHARED_MM_BUF
225 */
226 reg = <0x00000000 0x80000000 0 0x7fbf0000>,
227 <0x00000080 0x80000000 0 0x80000000>;
228 };
229
230 timer {
231 compatible = "arm,armv8-timer";
232 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
233 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
234 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
235 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
236 };
237
238 soc_clk24mhz: clk24mhz {
239 compatible = "fixed-clock";
240 #clock-cells = <0>;
241 clock-frequency = <24000000>;
242 clock-output-names = "refclk24mhz";
243 };
244
245 soc_refclk1mhz: refclk1mhz {
246 compatible = "fixed-clock";
247 #clock-cells = <0>;
248 clock-frequency = <1000000>;
249 clock-output-names = "refclk1mhz";
250 };
251
252 soc {
253 compatible = "simple-bus";
254 #address-cells = <2>;
255 #size-cells = <2>;
256 ranges;
257
258 gic: interrupt-controller@30000000 {
259 compatible = "arm,gic-v3";
260 reg = <0x0 0x30000000 0 0x10000>, // GICD
261 <0x0 0x301c0000 0 0x8000000>; // GICR
262 #interrupt-cells = <3>;
263 #address-cells = <2>;
264 #size-cells = <2>;
265 ranges;
266 interrupt-controller;
267 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
268
269 its1: msi-controller@30040000 {
270 compatible = "arm,gic-v3-its";
271 reg = <0x0 0x30040000 0x0 0x40000>;
272 msi-controller;
273 #msi-cells = <1>;
274 };
275 its2: msi-controller@30080000 {
276 compatible = "arm,gic-v3-its";
277 reg = <0x0 0x30080000 0x0 0x40000>;
278 msi-controller;
279 #msi-cells = <1>;
280 };
281 its3: msi-controller@300c0000 {
282 compatible = "arm,gic-v3-its";
283 reg = <0x0 0x300c0000 0x0 0x40000>;
284 msi-controller;
285 #msi-cells = <1>;
286 };
287 its4: msi-controller@30100000 {
288 compatible = "arm,gic-v3-its";
289 reg = <0x0 0x30100000 0x0 0x40000>;
290 msi-controller;
291 #msi-cells = <1>;
292 };
293 its5: msi-controller@30140000 {
294 compatible = "arm,gic-v3-its";
295 reg = <0x0 0x30140000 0x0 0x40000>;
296 msi-controller;
297 #msi-cells = <1>;
298 };
299 its6: msi-controller@30180000 {
300 compatible = "arm,gic-v3-its";
301 reg = <0x0 0x30180000 0x0 0x40000>;
302 msi-controller;
303 #msi-cells = <1>;
304 };
305 };
306
307 soc_serial0: serial@2a400000 {
308 compatible = "arm,pl011", "arm,primecell";
309 reg = <0x0 0x2a400000 0x0 0x10000>;
310 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
312 clock-names = "uartclk", "apb_pclk";
313 };
314
315 watchdog@2a440000 {
316 compatible = "arm,sbsa-gwdt";
317 reg = <0x0 0x2a440000 0 0x1000>,
318 <0x0 0x2a450000 0 0x1000>;
319 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
320 };
321
322 rtc@c170000 {
323 compatible = "arm,pl031", "arm,primecell";
324 reg = <0x0 0x0c170000 0x0 0x10000>;
325 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&soc_clk24mhz>;
327 clock-names = "apb_pclk";
328 };
329
330 virtio-net@c150000 {
331 compatible = "virtio,mmio";
332 reg = <0x0 0xc150000 0x0 0x200>;
333 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
334 };
335
336 virtio-block@c130000 {
337 compatible = "virtio,mmio";
338 reg = <0x0 0xc130000 0x0 0x200>;
339 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
340 };
341
342 virtio-rng@c140000 {
343 compatible = "virtio,mmio";
344 reg = <0x0 0xc140000 0x0 0x200>;
345 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
346 };
347
348 pci@4000000000 {
349 #address-cells = <0x03>;
350 #size-cells = <0x02>;
351 compatible = "pci-host-ecam-generic";
352 device_type = "pci";
353 bus-range = <0x00 0x11>;
354 reg = <0x40 0x00 0x00 0x04000000>;
355 ranges = <0x43000000 0x40 0x40000000 0x40 0x40000000 0x10 0x00000000
356 0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x08000000
357 0x01000000 0x00 0x00 0x00 0x77800000 0x00 0x800000>;
358 msi-map = <0x00 &its1 0x40000 0x10000>;
359 iommu-map = <0x00 &smmu 0x40000 0x10000>;
360 dma-coherent;
361 };
362
363 smmu: iommu@280000000 {
364 compatible = "arm,smmu-v3";
365 reg = <0x2 0x80000000 0x0 0x100000>;
366 dma-coherent;
367 #iommu-cells = <1>;
368 interrupts = <1 210 1>,
369 <1 211 1>,
370 <1 212 1>,
371 <1 213 1>;
372 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
373 msi-parent = <&its1 0x10000>;
374 };
375
376 sysreg: sysreg@c010000 {
377 compatible = "arm,vexpress-sysreg";
378 reg = <0x0 0xc010000 0x0 0x1000>;
379 gpio-controller;
380 #gpio-cells = <2>;
381 };
382
383 fixed_3v3: v2m-3v3@c011000 {
384 compatible = "regulator-fixed";
385 reg = <0x0 0xc011000 0x0 0x1000>;
386 regulator-name = "3V3";
387 regulator-min-microvolt = <3300000>;
388 regulator-max-microvolt = <3300000>;
389 regulator-always-on;
390 };
391
392 mmci@c050000 {
393 compatible = "arm,pl180", "arm,primecell";
394 reg = <0x0 0xc050000 0x0 0x1000>;
395 interrupts = <0 0x8B 0x4>,
396 <0 0x8C 0x4>;
397 cd-gpios = <&sysreg 0 0>;
398 wp-gpios = <&sysreg 1 0>;
399 bus-width = <8>;
400 max-frequency = <12000000>;
401 vmmc-supply = <&fixed_3v3>;
402 clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
403 clock-names = "mclk", "apb_pclk";
404 };
405
406 };
407
408 psci {
409 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
410 method = "smc";
411 cpu_suspend = <0xc4000001>;
412 cpu_off = <0x84000002>;
413 cpu_on = <0x84000003>;
414 };
415
416};