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Yann Gautiera3f46382023-06-14 10:40:59 +02001#
Yann Gautiera585d762024-01-03 14:28:23 +01002# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
Yann Gautiera3f46382023-06-14 10:40:59 +02003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Yann Gautier605facb2023-01-05 14:34:37 +01007# Extra partitions used to find FIP, contains:
8# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2).
9STM32_EXTRA_PARTS := 6
10
Yann Gautiera3f46382023-06-14 10:40:59 +020011include plat/st/common/common.mk
12
13CRASH_REPORTING := 1
14ENABLE_PIE := 1
15PROGRAMMABLE_RESET_ADDRESS := 1
Yann Gautier8053f2b2024-05-21 11:46:59 +020016BL2_IN_XIP_MEM := 1
Yann Gautiera3f46382023-06-14 10:40:59 +020017
18# Default Device tree
19DTB_FILE_NAME ?= stm32mp257f-ev1.dtb
20
21STM32MP25 := 1
22
23# STM32 image header version v2.2
24STM32_HEADER_VERSION_MAJOR := 2
25STM32_HEADER_VERSION_MINOR := 2
26
Yann Gautier7d13b4e2024-02-02 17:07:20 +010027# Set load address for serial boot devices
Yann Gautier8053f2b2024-05-21 11:46:59 +020028DWL_BUFFER_BASE ?= 0x87000000
Yann Gautier7d13b4e2024-02-02 17:07:20 +010029
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +020030# DDR types
31STM32MP_DDR3_TYPE ?= 0
32STM32MP_DDR4_TYPE ?= 0
33STM32MP_LPDDR4_TYPE ?= 0
34ifeq (${STM32MP_DDR3_TYPE},1)
35DDR_TYPE := ddr3
36endif
37ifeq (${STM32MP_DDR4_TYPE},1)
38DDR_TYPE := ddr4
39endif
40ifeq (${STM32MP_LPDDR4_TYPE},1)
41DDR_TYPE := lpddr4
42endif
43
Maxime Méréb151f682024-09-13 17:57:58 +020044# DDR features
45STM32MP_DDR_FIP_IO_STORAGE := 1
46
Yann Gautier626ec9d2023-06-14 18:44:41 +020047# Device tree
48BL2_DTSI := stm32mp25-bl2.dtsi
49FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
50
51# Macros and rules to build TF binary
52STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
53STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S
54STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S
55
Yann Gautier99f41322024-05-22 16:16:59 +020056STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME))
57STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME)
Maxime Méréb151f682024-09-13 17:57:58 +020058ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
59STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2
60STM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin
61STM32MP_DDR_FW := ${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME}
62endif
Yann Gautier99f41322024-05-22 16:16:59 +020063FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME)))
64# Add the FW_CONFIG to FIP and specify the same to certtool
65$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config))
Maxime Méréb151f682024-09-13 17:57:58 +020066ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
67# Add the FW_DDR to FIP and specify the same to certtool
68$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw))
69endif
Yann Gautier99f41322024-05-22 16:16:59 +020070
Yann Gautier8053f2b2024-05-21 11:46:59 +020071# Enable flags for C files
72$(eval $(call assert_booleans,\
73 $(sort \
Maxime Méréb151f682024-09-13 17:57:58 +020074 STM32MP_DDR_FIP_IO_STORAGE \
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +020075 STM32MP_DDR3_TYPE \
76 STM32MP_DDR4_TYPE \
77 STM32MP_LPDDR4_TYPE \
Yann Gautier8053f2b2024-05-21 11:46:59 +020078 STM32MP25 \
79)))
80
81$(eval $(call assert_numerics,\
82 $(sort \
83 PLAT_PARTITION_MAX_ENTRIES \
84 STM32_HEADER_VERSION_MAJOR \
85 STM32_TF_A_COPIES \
86)))
87
Yann Gautier7d13b4e2024-02-02 17:07:20 +010088$(eval $(call add_defines,\
89 $(sort \
90 DWL_BUFFER_BASE \
Maxime Méréb151f682024-09-13 17:57:58 +020091 PLAT_DEF_FIP_UUID \
Yann Gautier8053f2b2024-05-21 11:46:59 +020092 PLAT_PARTITION_MAX_ENTRIES \
93 PLAT_TBBR_IMG_DEF \
94 STM32_TF_A_COPIES \
Maxime Méréb151f682024-09-13 17:57:58 +020095 STM32MP_DDR_FIP_IO_STORAGE \
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +020096 STM32MP_DDR3_TYPE \
97 STM32MP_DDR4_TYPE \
98 STM32MP_LPDDR4_TYPE \
Yann Gautier8053f2b2024-05-21 11:46:59 +020099 STM32MP25 \
Yann Gautier7d13b4e2024-02-02 17:07:20 +0100100)))
101
Yann Gautiera3f46382023-06-14 10:40:59 +0200102# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI
103# Disable mbranch-protection to avoid adding useless code
104TF_CFLAGS += -mbranch-protection=none
105
106# Include paths and source files
107PLAT_INCLUDES += -Iplat/st/stm32mp2/include/
108
109PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S
Yann Gautiereb91af52023-06-14 18:05:47 +0200110PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
Yann Gautiera3f46382023-06-14 10:40:59 +0200111PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
112
Yann Gautier8053f2b2024-05-21 11:46:59 +0200113PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c
114
Gabriel Fernandez30437432022-04-20 10:08:08 +0200115PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \
Yann Gautierd58a3d22024-05-21 12:05:43 +0200116 drivers/st/reset/stm32mp2_reset.c \
117 plat/st/stm32mp2/stm32mp2_syscfg.c
Yann Gautiera585d762024-01-03 14:28:23 +0100118
Gabriel Fernandezbcd95062022-04-20 10:08:49 +0200119PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \
120 drivers/st/clk/clk-stm32mp2.c
121
Yann Gautiera3f46382023-06-14 10:40:59 +0200122BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c
Yann Gautier8053f2b2024-05-21 11:46:59 +0200123
Yann Gautiera3f46382023-06-14 10:40:59 +0200124BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c
125
Yann Gautier8053f2b2024-05-21 11:46:59 +0200126ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),)
127BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c
128endif
129
Yann Gautier7d13b4e2024-02-02 17:07:20 +0100130ifeq (${STM32MP_USB_PROGRAMMER},1)
131BL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c
132endif
133
Yann Gautier40ff1382024-05-21 20:54:04 +0200134BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr_helpers.c
135
Yann Gautierece4c252023-06-13 18:45:03 +0200136# BL31 sources
137BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
138
139BL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \
140 plat/st/stm32mp2/stm32mp2_pm.c \
141 plat/st/stm32mp2/stm32mp2_topology.c
142# Generic GIC v2
143include drivers/arm/gic/v2/gicv2.mk
144
145BL31_SOURCES += ${GICV2_SOURCES} \
146 plat/common/plat_gicv2.c \
147 plat/st/common/stm32mp_gic.c
148
149# Generic PSCI
150BL31_SOURCES += plat/common/plat_psci_common.c
151
Yann Gautier8053f2b2024-05-21 11:46:59 +0200152# Compilation rules
Nicolas Le Bayoncaff04c2021-07-05 15:23:54 +0200153.PHONY: check_ddr_type
154.SUFFIXES:
155
156bl2: check_ddr_type
157
158check_ddr_type:
159 $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \
160 $(STM32MP_DDR4_TYPE) + \
161 $(STM32MP_LPDDR4_TYPE)))))
162 @if [ ${DDR_TYPE} != 1 ]; then \
163 echo "One and only one DDR type must be defined"; \
164 false; \
165 fi
166
Yann Gautiera3f46382023-06-14 10:40:59 +0200167include plat/st/common/common_rules.mk