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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Jolly Shah6a903472019-08-27 11:23:08 -07002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08005 */
6
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +05307#include <stdbool.h>
8#include <string.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <common/debug.h>
11#include <drivers/generic_delay_timer.h>
12#include <lib/mmio.h>
13#include <lib/xlat_tables/xlat_tables.h>
Jolly Shah6a903472019-08-27 11:23:08 -070014#include <plat_ipi.h>
Jolly Shah0bfd7002019-01-08 11:10:47 -080015#include <plat_private.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <plat/common/platform.h>
17
Siva Durga Prasad Paladugu00ae6c52017-02-20 17:55:50 +053018#include "pm_api_sys.h"
Soren Brinkmann76fcae32016-03-06 20:16:27 -080019
20/*
21 * Table of regions to map using the MMU.
22 * This doesn't include TZRAM as the 'mem_layout' argument passed to
23 * configure_mmu_elx() will give the available subset of that,
24 */
25const mmap_region_t plat_arm_mmap[] = {
26 { DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
27 { DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
28 { CRF_APB_BASE, CRF_APB_BASE, CRF_APB_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
29 {0}
30};
31
32static unsigned int zynqmp_get_silicon_ver(void)
33{
Soren Brinkmann85863992016-09-16 10:34:47 -070034 static unsigned int ver;
Soren Brinkmann76fcae32016-03-06 20:16:27 -080035
Soren Brinkmann85863992016-09-16 10:34:47 -070036 if (!ver) {
37 ver = mmio_read_32(ZYNQMP_CSU_BASEADDR +
38 ZYNQMP_CSU_VERSION_OFFSET);
39 ver &= ZYNQMP_SILICON_VER_MASK;
40 ver >>= ZYNQMP_SILICON_VER_SHIFT;
41 }
Soren Brinkmann76fcae32016-03-06 20:16:27 -080042
43 return ver;
44}
45
46unsigned int zynqmp_get_uart_clk(void)
47{
48 unsigned int ver = zynqmp_get_silicon_ver();
49
Siva Durga Prasad Paladugudff07122018-09-04 18:02:25 +053050 if (ver == ZYNQMP_CSU_VERSION_QEMU)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080051 return 133000000;
Siva Durga Prasad Paladugudff07122018-09-04 18:02:25 +053052 else
53 return 100000000;
Soren Brinkmann76fcae32016-03-06 20:16:27 -080054}
55
Soren Brinkmann76fcae32016-03-06 20:16:27 -080056#if LOG_LEVEL >= LOG_LEVEL_NOTICE
57static const struct {
58 unsigned int id;
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +053059 unsigned int ver;
Soren Brinkmann76fcae32016-03-06 20:16:27 -080060 char *name;
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +053061 bool evexists;
Soren Brinkmann76fcae32016-03-06 20:16:27 -080062} zynqmp_devices[] = {
63 {
64 .id = 0x10,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -060065 .name = "XCZU3EG",
Soren Brinkmann76fcae32016-03-06 20:16:27 -080066 },
67 {
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +053068 .id = 0x10,
69 .ver = 0x2c,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -060070 .name = "XCZU3CG",
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +053071 },
72 {
Soren Brinkmann76fcae32016-03-06 20:16:27 -080073 .id = 0x11,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -060074 .name = "XCZU2EG",
Soren Brinkmann76fcae32016-03-06 20:16:27 -080075 },
76 {
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +053077 .id = 0x11,
78 .ver = 0x2c,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -060079 .name = "XCZU2CG",
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +053080 },
81 {
Soren Brinkmann76fcae32016-03-06 20:16:27 -080082 .id = 0x20,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -060083 .name = "XCZU5EV",
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +053084 .evexists = true,
Soren Brinkmann76fcae32016-03-06 20:16:27 -080085 },
86 {
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +053087 .id = 0x20,
88 .ver = 0x100,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -060089 .name = "XCZU5EG",
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +053090 .evexists = true,
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +053091 },
92 {
93 .id = 0x20,
94 .ver = 0x12c,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -060095 .name = "XCZU5CG",
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +053096 },
97 {
Soren Brinkmann76fcae32016-03-06 20:16:27 -080098 .id = 0x21,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -060099 .name = "XCZU4EV",
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530100 .evexists = true,
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800101 },
102 {
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +0530103 .id = 0x21,
104 .ver = 0x100,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600105 .name = "XCZU4EG",
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530106 .evexists = true,
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +0530107 },
108 {
109 .id = 0x21,
110 .ver = 0x12c,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600111 .name = "XCZU4CG",
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +0530112 },
113 {
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800114 .id = 0x30,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600115 .name = "XCZU7EV",
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530116 .evexists = true,
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800117 },
118 {
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +0530119 .id = 0x30,
120 .ver = 0x100,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600121 .name = "XCZU7EG",
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530122 .evexists = true,
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +0530123 },
124 {
125 .id = 0x30,
126 .ver = 0x12c,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600127 .name = "XCZU7CG",
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +0530128 },
129 {
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800130 .id = 0x38,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600131 .name = "XCZU9EG",
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800132 },
133 {
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +0530134 .id = 0x38,
135 .ver = 0x2c,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600136 .name = "XCZU9CG",
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +0530137 },
138 {
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800139 .id = 0x39,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600140 .name = "XCZU6EG",
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800141 },
142 {
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +0530143 .id = 0x39,
144 .ver = 0x2c,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600145 .name = "XCZU6CG",
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +0530146 },
147 {
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800148 .id = 0x40,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600149 .name = "XCZU11EG",
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800150 },
151 {
152 .id = 0x50,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600153 .name = "XCZU15EG",
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800154 },
155 {
156 .id = 0x58,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600157 .name = "XCZU19EG",
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800158 },
159 {
160 .id = 0x59,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600161 .name = "XCZU17EG",
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800162 },
Siva Durga Prasad Paladugu19d69c02017-06-06 12:54:52 +0530163 {
164 .id = 0x60,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600165 .name = "XCZU28DR",
Siva Durga Prasad Paladugu19d69c02017-06-06 12:54:52 +0530166 },
167 {
168 .id = 0x61,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600169 .name = "XCZU21DR",
Siva Durga Prasad Paladugu19d69c02017-06-06 12:54:52 +0530170 },
171 {
172 .id = 0x62,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600173 .name = "XCZU29DR",
Siva Durga Prasad Paladugu19d69c02017-06-06 12:54:52 +0530174 },
175 {
176 .id = 0x63,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600177 .name = "XCZU23DR",
Siva Durga Prasad Paladugu19d69c02017-06-06 12:54:52 +0530178 },
179 {
180 .id = 0x64,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600181 .name = "XCZU27DR",
Siva Durga Prasad Paladugu19d69c02017-06-06 12:54:52 +0530182 },
183 {
184 .id = 0x65,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600185 .name = "XCZU25DR",
Siva Durga Prasad Paladugu19d69c02017-06-06 12:54:52 +0530186 },
Siva Durga Prasad Paladugu32267282019-03-23 15:26:31 +0530187 {
188 .id = 0x66,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600189 .name = "XCZU39DR",
Siva Durga Prasad Paladugu32267282019-03-23 15:26:31 +0530190 },
Venkatesh Yadav Abbarapu927c2b92019-07-30 11:12:55 +0530191 {
Venkatesh Yadav Abbarapu5a3226c2021-03-03 00:43:16 -0700192 .id = 0x7d,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600193 .name = "XCZU43DR",
Venkatesh Yadav Abbarapu5a3226c2021-03-03 00:43:16 -0700194 },
195 {
196 .id = 0x78,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600197 .name = "XCZU46DR",
Venkatesh Yadav Abbarapu5a3226c2021-03-03 00:43:16 -0700198 },
199 {
200 .id = 0x7f,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600201 .name = "XCZU47DR",
Venkatesh Yadav Abbarapu5a3226c2021-03-03 00:43:16 -0700202 },
203 {
Venkatesh Yadav Abbarapu927c2b92019-07-30 11:12:55 +0530204 .id = 0x7b,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600205 .name = "XCZU48DR",
Venkatesh Yadav Abbarapu927c2b92019-07-30 11:12:55 +0530206 },
207 {
208 .id = 0x7e,
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600209 .name = "XCZU49DR",
Venkatesh Yadav Abbarapu927c2b92019-07-30 11:12:55 +0530210 },
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800211};
212
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530213#define ZYNQMP_PL_STATUS_BIT 9
214#define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
215#define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
216
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600217#define SILICON_ID_XCK26 0x4724093
218
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530219static char *zynqmp_get_silicon_idcode_name(void)
Soren Brinkmanncb366812016-09-22 12:21:11 -0700220{
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530221 uint32_t id, ver, chipid[2];
222 size_t i, j, len;
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530223 const char *name = "EG/EV";
Soren Brinkmanncb366812016-09-22 12:21:11 -0700224
Siva Durga Prasad Paladugu6a8933c2018-06-20 17:03:57 +0530225#ifdef IMAGE_BL32
226 /*
227 * For BL32, get the chip id info directly by reading corresponding
228 * registers instead of making pm call. This has limitation
229 * that these registers should be configured to have access
230 * from APU which is default case.
231 */
232 chipid[0] = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
233 chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET);
234#else
235 if (pm_get_chipid(chipid) != PM_RET_SUCCESS)
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600236 return "XCZUUNKN";
Siva Durga Prasad Paladugu6a8933c2018-06-20 17:03:57 +0530237#endif
Soren Brinkmanncb366812016-09-22 12:21:11 -0700238
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530239 id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
240 ZYNQMP_CSU_IDCODE_SVD_MASK);
Soren Brinkmanncb366812016-09-22 12:21:11 -0700241 id >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530242 ver = chipid[1] >> ZYNQMP_EFUSE_IPDISABLE_SHIFT;
Soren Brinkmanncb366812016-09-22 12:21:11 -0700243
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530244 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
245 if (zynqmp_devices[i].id == id &&
246 zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK))
247 break;
248 }
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +0530249
Venkatesh Yadav Abbarapufcfdaf02021-04-21 21:54:48 -0600250 if (i >= ARRAY_SIZE(zynqmp_devices)) {
251 if (chipid[0] == SILICON_ID_XCK26) {
252 return "XCK26";
253 } else {
254 return "XCZUUNKN";
255 }
256 }
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +0530257
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530258 if (!zynqmp_devices[i].evexists)
259 return zynqmp_devices[i].name;
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800260
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530261 if (ver & ZYNQMP_PL_STATUS_MASK)
262 return zynqmp_devices[i].name;
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +0530263
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530264 len = strlen(zynqmp_devices[i].name) - 2;
265 for (j = 0; j < strlen(name); j++) {
266 zynqmp_devices[i].name[len] = name[j];
267 len++;
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800268 }
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530269 zynqmp_devices[i].name[len] = '\0';
270
271 return zynqmp_devices[i].name;
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800272}
273
274static unsigned int zynqmp_get_rtl_ver(void)
275{
276 uint32_t ver;
277
278 ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);
279 ver &= ZYNQMP_RTL_VER_MASK;
280 ver >>= ZYNQMP_RTL_VER_SHIFT;
281
282 return ver;
283}
284
285static char *zynqmp_print_silicon_idcode(void)
286{
287 uint32_t id, maskid, tmp;
288
289 id = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
290
291 tmp = id;
292 tmp &= ZYNQMP_CSU_IDCODE_XILINX_ID_MASK |
Soren Brinkmann31114132016-05-20 07:05:00 -0700293 ZYNQMP_CSU_IDCODE_FAMILY_MASK;
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800294 maskid = ZYNQMP_CSU_IDCODE_XILINX_ID << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT |
Soren Brinkmann31114132016-05-20 07:05:00 -0700295 ZYNQMP_CSU_IDCODE_FAMILY << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT;
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800296 if (tmp != maskid) {
297 ERROR("Incorrect XILINX IDCODE 0x%x, maskid 0x%x\n", id, maskid);
298 return "UNKN";
299 }
300 VERBOSE("Xilinx IDCODE 0x%x\n", id);
301 return zynqmp_get_silicon_idcode_name();
302}
303
304static unsigned int zynqmp_get_ps_ver(void)
305{
306 uint32_t ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);
307
308 ver &= ZYNQMP_PS_VER_MASK;
309 ver >>= ZYNQMP_PS_VER_SHIFT;
310
311 return ver + 1;
312}
313
314static void zynqmp_print_platform_name(void)
315{
316 unsigned int ver = zynqmp_get_silicon_ver();
317 unsigned int rtl = zynqmp_get_rtl_ver();
318 char *label = "Unknown";
319
320 switch (ver) {
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800321 case ZYNQMP_CSU_VERSION_QEMU:
322 label = "QEMU";
323 break;
324 case ZYNQMP_CSU_VERSION_SILICON:
325 label = "silicon";
326 break;
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000327 default:
328 /* Do nothing in default case */
329 break;
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800330 }
331
Venkatesh Yadav Abbarapud4740e42021-06-17 00:23:52 -0600332 NOTICE("TF-A running on %s/%s at 0x%x\n",
333 zynqmp_print_silicon_idcode(), label, BL31_BASE);
334 VERBOSE("TF-A running on v%d/RTL%d.%d\n",
335 zynqmp_get_ps_ver(), (rtl & 0xf0) >> 4, rtl & 0xf);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800336}
337#else
338static inline void zynqmp_print_platform_name(void) { }
339#endif
340
Soren Brinkmannb43d9432016-04-18 11:49:42 -0700341unsigned int zynqmp_get_bootmode(void)
342{
Siva Durga Prasad Paladugu00ae6c52017-02-20 17:55:50 +0530343 uint32_t r;
Siva Durga Prasad Paladugu40808bc2018-04-30 19:43:03 +0530344 unsigned int ret;
Siva Durga Prasad Paladugu00ae6c52017-02-20 17:55:50 +0530345
Siva Durga Prasad Paladugu40808bc2018-04-30 19:43:03 +0530346 ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r);
347
348 if (ret != PM_RET_SUCCESS)
Siva Durga Prasad Paladugu00ae6c52017-02-20 17:55:50 +0530349 r = mmio_read_32(CRL_APB_BOOT_MODE_USER);
Soren Brinkmannb43d9432016-04-18 11:49:42 -0700350
351 return r & CRL_APB_BOOT_MODE_MASK;
352}
353
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800354void zynqmp_config_setup(void)
355{
Rajan Vaja12be18b2021-03-26 04:16:36 -0700356 uint64_t counter_freq;
357
Jolly Shah6a903472019-08-27 11:23:08 -0700358 /* Configure IPI data for ZynqMP */
359 zynqmp_ipi_config_table_init();
360
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800361 zynqmp_print_platform_name();
Rajan Vaja12be18b2021-03-26 04:16:36 -0700362
363 /* Configure counter frequency */
364 counter_freq = read_cntfrq_el0();
365 if (counter_freq == ZYNQMP_DEFAULT_COUNTER_FREQ) {
366 write_cntfrq_el0(plat_get_syscnt_freq2());
367 }
368
Soren Brinkmanne5bdcaa2016-06-22 09:02:56 -0700369 generic_delay_timer_init();
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800370}
371
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100372unsigned int plat_get_syscnt_freq2(void)
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800373{
Soren Brinkmanncfcb1a22016-09-16 10:31:06 -0700374 unsigned int ver = zynqmp_get_silicon_ver();
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800375
Siva Durga Prasad Paladugudff07122018-09-04 18:02:25 +0530376 if (ver == ZYNQMP_CSU_VERSION_QEMU)
Edgar E. Iglesias481d2c22019-04-17 15:21:28 +0200377 return 65000000;
Siva Durga Prasad Paladugudff07122018-09-04 18:02:25 +0530378 else
379 return mmio_read_32(IOU_SCNTRS_BASEFREQ);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800380}