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Usama Arifbec5afd2020-04-17 16:13:39 +01001/*
Boyan Karatotevffe75692023-11-29 15:27:18 +00002 * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
Usama Arifbec5afd2020-04-17 16:13:39 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8
9#include <libfdt.h>
Usama Ariff1513622021-04-09 17:07:41 +010010#include <tc_plat.h>
Usama Arifbec5afd2020-04-17 16:13:39 +010011
Manish V Badarkheb241efb2023-10-18 14:11:45 +010012#include <arch_helpers.h>
Usama Arifbec5afd2020-04-17 16:13:39 +010013#include <common/bl_common.h>
14#include <common/debug.h>
15#include <drivers/arm/css/css_mhu_doorbell.h>
16#include <drivers/arm/css/scmi.h>
Madhukar Pappireddye108df22023-03-22 15:40:40 -050017#include <drivers/arm/sbsa.h>
Usama Arifa49bd492021-08-17 17:57:10 +010018#include <lib/fconf/fconf.h>
19#include <lib/fconf/fconf_dyn_cfg_getter.h>
Usama Arifbec5afd2020-04-17 16:13:39 +010020#include <plat/arm/common/plat_arm.h>
21#include <plat/common/platform.h>
22
Manish V Badarkheb20ca822023-12-06 09:16:08 +000023#ifdef PLATFORM_TEST_TFM_TESTSUITE
Manish V Badarkheb241efb2023-10-18 14:11:45 +010024#include <psa/crypto_platform.h>
25#include <psa/crypto_types.h>
26#include <psa/crypto_values.h>
Manish V Badarkheb20ca822023-12-06 09:16:08 +000027#endif /* PLATFORM_TEST_TFM_TESTSUITE */
Manish V Badarkheb241efb2023-10-18 14:11:45 +010028
29#ifdef PLATFORM_TEST_TFM_TESTSUITE
30/*
31 * We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
32 * mbedTLS config option) so we need to provide an implementation of
33 * mbedtls_psa_external_get_random(). Provide a fake one, since we do not
34 * actually use any of external RNG and this function is only needed during
35 * the execution of TF-M testsuite during exporting the public part of the
36 * delegated attestation key.
37 */
38psa_status_t mbedtls_psa_external_get_random(
39 mbedtls_psa_external_random_context_t *context,
40 uint8_t *output, size_t output_size,
41 size_t *output_length)
42{
43 for (size_t i = 0U; i < output_size; i++) {
44 output[i] = (uint8_t)(read_cntpct_el0() & 0xFFU);
45 }
46
47 *output_length = output_size;
48
49 return PSA_SUCCESS;
50}
51#endif /* PLATFORM_TEST_TFM_TESTSUITE */
52
Leo Yan7d51bf82024-05-22 15:42:46 +010053#if TARGET_PLATFORM <= 2
Leo Yan8dd7d432024-05-22 15:41:37 +010054static scmi_channel_plat_info_t tc_scmi_plat_info = {
55 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
56 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
57 .db_preserve_mask = 0xfffffffe,
58 .db_modify_mask = 0x1,
59 .ring_doorbell = &mhuv2_ring_doorbell,
Usama Arifbec5afd2020-04-17 16:13:39 +010060};
Jackson Cooper-Driver3653ded2023-12-14 14:32:40 +000061#elif TARGET_PLATFORM >= 3
Leo Yan7d51bf82024-05-22 15:42:46 +010062static scmi_channel_plat_info_t tc_scmi_plat_info = {
63 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
64 .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0),
65 .db_preserve_mask = 0xfffffffe,
66 .db_modify_mask = 0x1,
67 .ring_doorbell = &mhu_ring_doorbell,
68};
Jackson Cooper-Driver3653ded2023-12-14 14:32:40 +000069#endif
Jagdish Gediya5ae7c382023-12-18 05:56:00 +000070
Jackson Cooper-Driver3653ded2023-12-14 14:32:40 +000071#if TARGET_PLATFORM == 3
Jagdish Gediya5ae7c382023-12-18 05:56:00 +000072static void enable_ns_mcn_pmu(void)
73{
74 /*
75 * Enable non-secure access to MCN PMU registers
76 */
77 for (int i = 0; i < MCN_INSTANCES; i++) {
78 uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR + MCN_SCR_OFFSET +
79 (i * MCN_ADDRESS_SPACE_SIZE);
80 mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT);
81 }
82}
Jagdish Gediyaebaa6bf2024-01-11 10:49:46 +000083
84static void set_mcn_slc_alloc_mode(void)
85{
86 /*
87 * SLC WRALLOCMODE and RDALLOCMODE are configured by default to
88 * 0b01 (always alloc), configure both to 0b10 (use bus signal
89 * attribute from interface).
90 */
91 for (int i = 0; i < MCN_INSTANCES; i++) {
92 uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR +
93 (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET;
94 uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR +
95 (i * MCN_ADDRESS_SPACE_SIZE) + MPAM_SLCCFG_CTL_OFFSET;
96
97 mmio_clrsetbits_32(slccfg_ctl_ns,
98 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK),
99 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) |
100 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT));
101 mmio_clrsetbits_32(slccfg_ctl_s,
102 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK),
103 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) |
104 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT));
105 }
106}
Leo Yan7d51bf82024-05-22 15:42:46 +0100107#endif
Usama Arifbec5afd2020-04-17 16:13:39 +0100108
109void bl31_platform_setup(void)
110{
Usama Ariff1513622021-04-09 17:07:41 +0100111 tc_bl31_common_platform_setup();
Jagdish Gediya5ae7c382023-12-18 05:56:00 +0000112#if TARGET_PLATFORM == 3
113 enable_ns_mcn_pmu();
Jagdish Gediyaebaa6bf2024-01-11 10:49:46 +0000114 set_mcn_slc_alloc_mode();
Jagdish Gediya16a0f1c2024-02-02 06:01:44 +0000115 plat_arm_ni_setup(NCI_BASE_ADDR);
Jagdish Gediya5ae7c382023-12-18 05:56:00 +0000116#endif
Usama Arifbec5afd2020-04-17 16:13:39 +0100117}
118
Leo Yan8dd7d432024-05-22 15:41:37 +0100119scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id __unused)
Usama Arifbec5afd2020-04-17 16:13:39 +0100120{
121
Leo Yan8dd7d432024-05-22 15:41:37 +0100122 return &tc_scmi_plat_info;
Usama Arifbec5afd2020-04-17 16:13:39 +0100123
124}
125
126void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
127 u_register_t arg2, u_register_t arg3)
128{
129 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
Usama Arifa49bd492021-08-17 17:57:10 +0100130
131 /* Fill the properties struct with the info from the config dtb */
132 fconf_populate("FW_CONFIG", arg1);
Usama Arifbec5afd2020-04-17 16:13:39 +0100133}
134
laurenw-arm4c4181c2023-05-04 14:55:37 -0500135#ifdef PLATFORM_TESTS
Sandrine Bailleux27fba522023-05-05 15:44:26 +0200136static __dead2 void tc_run_platform_tests(void)
Usama Arifbec5afd2020-04-17 16:13:39 +0100137{
Sandrine Bailleuxf0f42fb2023-05-05 15:59:00 +0200138 int tests_failed;
139
140 printf("\nStarting platform tests...\n");
Mate Toth-Pal14ba4af2022-10-21 14:24:49 +0200141
Tamas Ban15b79da2023-04-21 09:31:48 +0200142#ifdef PLATFORM_TEST_NV_COUNTERS
Sandrine Bailleuxf0f42fb2023-05-05 15:59:00 +0200143 tests_failed = nv_counter_test();
laurenw-arm116f10c2023-06-13 16:43:39 -0500144#elif PLATFORM_TEST_ROTPK
145 tests_failed = rotpk_test();
Tamas Ban15b79da2023-04-21 09:31:48 +0200146#elif PLATFORM_TEST_TFM_TESTSUITE
Sandrine Bailleuxf0f42fb2023-05-05 15:59:00 +0200147 tests_failed = run_platform_tests();
laurenw-arm2ce1e352023-02-07 13:40:05 -0600148#endif
Sandrine Bailleuxf0f42fb2023-05-05 15:59:00 +0200149
150 printf("Platform tests %s.\n",
151 (tests_failed != 0) ? "failed" : "succeeded");
152
Sandrine Bailleuxe1da6c42023-05-05 13:59:07 +0200153 /* Suspend booting, no matter the tests outcome. */
Sandrine Bailleuxf0f42fb2023-05-05 15:59:00 +0200154 printf("Suspend booting...\n");
Mate Toth-Pal14ba4af2022-10-21 14:24:49 +0200155 plat_error_handler(-1);
Sandrine Bailleux27fba522023-05-05 15:44:26 +0200156}
157#endif
158
159void tc_bl31_common_platform_setup(void)
160{
161 arm_bl31_platform_setup();
162
163#ifdef PLATFORM_TESTS
164 tc_run_platform_tests();
laurenw-arm481ac282023-05-03 12:48:55 -0500165#endif
Usama Arifbec5afd2020-04-17 16:13:39 +0100166}
167
168const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
169{
170 return css_scmi_override_pm_ops(ops);
171}
Usama Arifa49bd492021-08-17 17:57:10 +0100172
173void __init bl31_plat_arch_setup(void)
174{
175 arm_bl31_plat_arch_setup();
176
177 /* HW_CONFIG was also loaded by BL2 */
178 const struct dyn_cfg_dtb_info_t *hw_config_info;
179
180 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
181 assert(hw_config_info != NULL);
182
183 fconf_populate("HW_CONFIG", hw_config_info->config_addr);
184}
Madhukar Pappireddye108df22023-03-22 15:40:40 -0500185
Govindraj Raja436ea5e2023-05-10 14:50:36 -0500186#if defined(SPD_spmd) && (SPMC_AT_EL3 == 0)
Madhukar Pappireddye108df22023-03-22 15:40:40 -0500187void tc_bl31_plat_runtime_setup(void)
188{
Madhukar Pappireddye108df22023-03-22 15:40:40 -0500189 /* Start secure watchdog timer. */
190 plat_arm_secure_wdt_start();
Salman Nabi442b0752024-02-19 17:03:44 +0000191
192 arm_bl31_plat_runtime_setup();
Madhukar Pappireddye108df22023-03-22 15:40:40 -0500193}
194
195void bl31_plat_runtime_setup(void)
196{
197 tc_bl31_plat_runtime_setup();
198}
199
200/*
201 * Platform handler for Group0 secure interrupt.
202 */
203int plat_spmd_handle_group0_interrupt(uint32_t intid)
204{
205 /* Trusted Watchdog timer is the only source of Group0 interrupt now. */
206 if (intid == SBSA_SECURE_WDOG_INTID) {
Madhukar Pappireddye108df22023-03-22 15:40:40 -0500207 /* Refresh the timer. */
208 plat_arm_secure_wdt_refresh();
209
Madhukar Pappireddye108df22023-03-22 15:40:40 -0500210 return 0;
211 }
212
213 return -1;
214}
Govindraj Raja436ea5e2023-05-10 14:50:36 -0500215#endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/