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Usama Arifbec5afd2020-04-17 16:13:39 +01001/*
Jagdish Gediya4df2d372024-04-22 13:30:51 +00002 * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
Usama Arifbec5afd2020-04-17 16:13:39 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <platform_def.h>
10#include <cpu_macros.S>
11
Jagdish Gediya71d2d2b2024-07-17 15:34:28 +010012#define TC_HANDLER(rev) plat_reset_handler_tc##rev
13#define PLAT_RESET_HANDLER(rev) TC_HANDLER(rev)
14
Usama Arifbec5afd2020-04-17 16:13:39 +010015 .globl plat_arm_calc_core_pos
16 .globl plat_reset_handler
17
18 /* ---------------------------------------------------------------------
19 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
20 *
Usama Ariff1513622021-04-09 17:07:41 +010021 * Function to calculate the core position on TC.
Usama Arifbec5afd2020-04-17 16:13:39 +010022 *
23 * (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) +
24 * (CPUId * PLAT_MAX_PE_PER_CPU) +
25 * ThreadId
26 *
27 * which can be simplified as:
28 *
29 * ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU)
30 * + ThreadId
31 * ---------------------------------------------------------------------
32 */
33func plat_arm_calc_core_pos
34 /*
35 * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
36 * look as if in a multi-threaded implementation.
37 */
38 tst x0, #MPIDR_MT_MASK
39 lsl x3, x0, #MPIDR_AFFINITY_BITS
40 csel x3, x3, x0, eq
41
42 /* Extract individual affinity fields from MPIDR */
43 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
44 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
45 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
46
47 /* Compute linear position */
48 mov x4, #PLAT_MAX_CPUS_PER_CLUSTER
49 madd x1, x2, x4, x1
50 mov x5, #PLAT_MAX_PE_PER_CPU
51 madd x0, x1, x5, x0
52 ret
53endfunc plat_arm_calc_core_pos
54
Jagdish Gediyabfab8eb2024-07-23 15:41:34 +010055func mark_extllc_presence
56#ifdef MCN_CONFIG_ADDR
57 mov_imm x0, (MCN_CONFIG_ADDR)
58 ldr w1, [x0]
59 ubfx x1, x1, #MCN_CONFIG_SLC_PRESENT_BIT, #1
60 sysreg_bitfield_insert_from_gpr CPUECTLR_EL1, x1, \
61 CPUECTLR_EL1_EXTLLC_BIT, 1
62#endif
63 ret
64endfunc mark_extllc_presence
65
Jagdish Gediya71d2d2b2024-07-17 15:34:28 +010066func enable_dsu_pmu_el1_access
67 sysreg_bit_set actlr_el2, CPUACTLR_CLUSTERPMUEN
68 sysreg_bit_set actlr_el3, CPUACTLR_CLUSTERPMUEN
69 ret
70endfunc enable_dsu_pmu_el1_access
71
72func TC_HANDLER(2)
73 ret
74endfunc TC_HANDLER(2)
75
76func TC_HANDLER(3)
77 mov x9, lr
Jagdish Gediyabfab8eb2024-07-23 15:41:34 +010078 bl mark_extllc_presence
Jagdish Gediya71d2d2b2024-07-17 15:34:28 +010079 bl enable_dsu_pmu_el1_access
80 mov lr, x9
81 ret
82endfunc TC_HANDLER(3)
83
Usama Arifbec5afd2020-04-17 16:13:39 +010084 /* -----------------------------------------------------
85 * void plat_reset_handler(void);
Usama Arifbec5afd2020-04-17 16:13:39 +010086 * -----------------------------------------------------
87 */
88func plat_reset_handler
Jagdish Gediya71d2d2b2024-07-17 15:34:28 +010089 mov x8, lr
90 bl PLAT_RESET_HANDLER(TARGET_PLATFORM)
91 mov lr, x8
Usama Arifbec5afd2020-04-17 16:13:39 +010092 ret
93endfunc plat_reset_handler