blob: 9e34efba4c1018346fac43da2dbd21a44c7f2b38 [file] [log] [blame]
Alexei Fedorov48009432019-04-04 16:26:34 +01001/*
2 * Copyright (c) 2019, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef CORTEX_A76AE_H
8#define CORTEX_A76AE_H
9
10#include <lib/utils_def.h>
11
12/* Cortex-A76AE MIDR for revision 0 */
13#define CORTEX_A76AE_MIDR U(0x410FD0E0)
14
15/*******************************************************************************
16 * CPU Extended Control register specific definitions.
17 ******************************************************************************/
18#define CORTEX_A76AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7
19
20/* Definitions of register field mask in CORTEX_A76AE_CPUPWRCTLR_EL1 */
21#define CORTEX_A76AE_CORE_PWRDN_EN_MASK U(0x1)
22
23#define CORTEX_A76AE_CPUECTLR_EL1 S3_0_C15_C1_4
24
25#endif /* CORTEX_A76AE_H */