Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 6 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 7 | #include <asm_macros.S> |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 8 | #include <bl_common.h> |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 9 | #include <cortex_a53.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 10 | #include <cpu_macros.S> |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 11 | #include <debug.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 12 | #include <plat_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 13 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 14 | #if A53_DISABLE_NON_TEMPORAL_HINT |
| 15 | #undef ERRATA_A53_836870 |
| 16 | #define ERRATA_A53_836870 1 |
| 17 | #endif |
| 18 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 19 | /* --------------------------------------------- |
| 20 | * Disable L1 data cache and unified L2 cache |
| 21 | * --------------------------------------------- |
| 22 | */ |
| 23 | func cortex_a53_disable_dcache |
| 24 | mrs x1, sctlr_el3 |
| 25 | bic x1, x1, #SCTLR_C_BIT |
| 26 | msr sctlr_el3, x1 |
| 27 | isb |
| 28 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 29 | endfunc cortex_a53_disable_dcache |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 30 | |
| 31 | /* --------------------------------------------- |
| 32 | * Disable intra-cluster coherency |
| 33 | * --------------------------------------------- |
| 34 | */ |
| 35 | func cortex_a53_disable_smp |
| 36 | mrs x0, CPUECTLR_EL1 |
| 37 | bic x0, x0, #CPUECTLR_SMP_BIT |
| 38 | msr CPUECTLR_EL1, x0 |
| 39 | isb |
| 40 | dsb sy |
| 41 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 42 | endfunc cortex_a53_disable_smp |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 43 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 44 | /* -------------------------------------------------- |
| 45 | * Errata Workaround for Cortex A53 Errata #826319. |
| 46 | * This applies only to revision <= r0p2 of Cortex A53. |
| 47 | * Inputs: |
| 48 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 49 | * Shall clobber: x0-x17 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 50 | * -------------------------------------------------- |
| 51 | */ |
| 52 | func errata_a53_826319_wa |
| 53 | /* |
| 54 | * Compare x0 against revision r0p2 |
| 55 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 56 | mov x17, x30 |
| 57 | bl check_errata_826319 |
| 58 | cbz x0, 1f |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 59 | mrs x1, L2ACTLR_EL1 |
| 60 | bic x1, x1, #L2ACTLR_ENABLE_UNIQUECLEAN |
| 61 | orr x1, x1, #L2ACTLR_DISABLE_CLEAN_PUSH |
| 62 | msr L2ACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 63 | 1: |
| 64 | ret x17 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 65 | endfunc errata_a53_826319_wa |
| 66 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 67 | func check_errata_826319 |
| 68 | mov x1, #0x02 |
| 69 | b cpu_rev_var_ls |
| 70 | endfunc check_errata_826319 |
| 71 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 72 | /* --------------------------------------------------------------------- |
| 73 | * Disable the cache non-temporal hint. |
| 74 | * |
| 75 | * This ignores the Transient allocation hint in the MAIR and treats |
| 76 | * allocations the same as non-transient allocation types. As a result, |
| 77 | * the LDNP and STNP instructions in AArch64 behave the same as the |
| 78 | * equivalent LDP and STP instructions. |
| 79 | * |
| 80 | * This is relevant only for revisions <= r0p3 of Cortex-A53. |
| 81 | * From r0p4 and onwards, the bit to disable the hint is enabled by |
| 82 | * default at reset. |
| 83 | * |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 84 | * Inputs: |
| 85 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 86 | * Shall clobber: x0-x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 87 | * --------------------------------------------------------------------- |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 88 | */ |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 89 | func a53_disable_non_temporal_hint |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 90 | /* |
| 91 | * Compare x0 against revision r0p3 |
| 92 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 93 | mov x17, x30 |
| 94 | bl check_errata_disable_non_temporal_hint |
| 95 | cbz x0, 1f |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 96 | mrs x1, CPUACTLR_EL1 |
| 97 | orr x1, x1, #CPUACTLR_DTAH |
| 98 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 99 | 1: |
| 100 | ret x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 101 | endfunc a53_disable_non_temporal_hint |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 102 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 103 | func check_errata_disable_non_temporal_hint |
| 104 | mov x1, #0x03 |
| 105 | b cpu_rev_var_ls |
| 106 | endfunc check_errata_disable_non_temporal_hint |
| 107 | |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 108 | /* -------------------------------------------------- |
| 109 | * Errata Workaround for Cortex A53 Errata #855873. |
| 110 | * |
| 111 | * This applies only to revisions >= r0p3 of Cortex A53. |
| 112 | * Earlier revisions of the core are affected as well, but don't |
| 113 | * have the chicken bit in the CPUACTLR register. It is expected that |
| 114 | * the rich OS takes care of that, especially as the workaround is |
| 115 | * shared with other erratas in those revisions of the CPU. |
| 116 | * Inputs: |
| 117 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 118 | * Shall clobber: x0-x17 |
| 119 | * -------------------------------------------------- |
| 120 | */ |
| 121 | func errata_a53_855873_wa |
| 122 | /* |
| 123 | * Compare x0 against revision r0p3 and higher |
| 124 | */ |
| 125 | mov x17, x30 |
| 126 | bl check_errata_855873 |
| 127 | cbz x0, 1f |
| 128 | |
| 129 | mrs x1, CPUACTLR_EL1 |
| 130 | orr x1, x1, #CPUACTLR_ENDCCASCI |
| 131 | msr CPUACTLR_EL1, x1 |
| 132 | 1: |
| 133 | ret x17 |
| 134 | endfunc errata_a53_855873_wa |
| 135 | |
| 136 | func check_errata_855873 |
| 137 | mov x1, #0x03 |
| 138 | b cpu_rev_var_hs |
| 139 | endfunc check_errata_855873 |
| 140 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 141 | /* ------------------------------------------------- |
| 142 | * The CPU Ops reset function for Cortex-A53. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 143 | * Shall clobber: x0-x19 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 144 | * ------------------------------------------------- |
| 145 | */ |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 146 | func cortex_a53_reset_func |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 147 | mov x19, x30 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 148 | bl cpu_get_rev_var |
| 149 | mov x18, x0 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 150 | |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 151 | |
| 152 | #if ERRATA_A53_826319 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 153 | mov x0, x18 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 154 | bl errata_a53_826319_wa |
| 155 | #endif |
| 156 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 157 | #if ERRATA_A53_836870 |
| 158 | mov x0, x18 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 159 | bl a53_disable_non_temporal_hint |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 160 | #endif |
| 161 | |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 162 | #if ERRATA_A53_855873 |
| 163 | mov x0, x18 |
| 164 | bl errata_a53_855873_wa |
| 165 | #endif |
| 166 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 167 | /* --------------------------------------------- |
Sandrine Bailleux | f12a31d | 2016-01-29 14:37:58 +0000 | [diff] [blame] | 168 | * Enable the SMP bit. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 169 | * --------------------------------------------- |
| 170 | */ |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 171 | mrs x0, CPUECTLR_EL1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 172 | orr x0, x0, #CPUECTLR_SMP_BIT |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 173 | msr CPUECTLR_EL1, x0 |
developer | 4fceaca | 2015-07-29 20:55:31 +0800 | [diff] [blame] | 174 | isb |
| 175 | ret x19 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 176 | endfunc cortex_a53_reset_func |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 177 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 178 | func cortex_a53_core_pwr_dwn |
| 179 | mov x18, x30 |
| 180 | |
| 181 | /* --------------------------------------------- |
| 182 | * Turn off caches. |
| 183 | * --------------------------------------------- |
| 184 | */ |
| 185 | bl cortex_a53_disable_dcache |
| 186 | |
| 187 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 188 | * Flush L1 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 189 | * --------------------------------------------- |
| 190 | */ |
| 191 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 192 | bl dcsw_op_level1 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 193 | |
| 194 | /* --------------------------------------------- |
| 195 | * Come out of intra cluster coherency |
| 196 | * --------------------------------------------- |
| 197 | */ |
| 198 | mov x30, x18 |
| 199 | b cortex_a53_disable_smp |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 200 | endfunc cortex_a53_core_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 201 | |
| 202 | func cortex_a53_cluster_pwr_dwn |
| 203 | mov x18, x30 |
| 204 | |
| 205 | /* --------------------------------------------- |
| 206 | * Turn off caches. |
| 207 | * --------------------------------------------- |
| 208 | */ |
| 209 | bl cortex_a53_disable_dcache |
| 210 | |
| 211 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 212 | * Flush L1 caches. |
| 213 | * --------------------------------------------- |
| 214 | */ |
| 215 | mov x0, #DCCISW |
| 216 | bl dcsw_op_level1 |
| 217 | |
| 218 | /* --------------------------------------------- |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 219 | * Disable the optional ACP. |
| 220 | * --------------------------------------------- |
| 221 | */ |
| 222 | bl plat_disable_acp |
| 223 | |
| 224 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 225 | * Flush L2 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 226 | * --------------------------------------------- |
| 227 | */ |
| 228 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 229 | bl dcsw_op_level2 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 230 | |
| 231 | /* --------------------------------------------- |
| 232 | * Come out of intra cluster coherency |
| 233 | * --------------------------------------------- |
| 234 | */ |
| 235 | mov x30, x18 |
| 236 | b cortex_a53_disable_smp |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 237 | endfunc cortex_a53_cluster_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 238 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 239 | #if REPORT_ERRATA |
| 240 | /* |
| 241 | * Errata printing function for Cortex A53. Must follow AAPCS. |
| 242 | */ |
| 243 | func cortex_a53_errata_report |
| 244 | stp x8, x30, [sp, #-16]! |
| 245 | |
| 246 | bl cpu_get_rev_var |
| 247 | mov x8, x0 |
| 248 | |
| 249 | /* |
| 250 | * Report all errata. The revision-variant information is passed to |
| 251 | * checking functions of each errata. |
| 252 | */ |
| 253 | report_errata ERRATA_A53_826319, cortex_a53, 826319 |
| 254 | report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 255 | report_errata ERRATA_A53_855873, cortex_a53, 855873 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 256 | |
| 257 | ldp x8, x30, [sp], #16 |
| 258 | ret |
| 259 | endfunc cortex_a53_errata_report |
| 260 | #endif |
| 261 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 262 | /* --------------------------------------------- |
| 263 | * This function provides cortex_a53 specific |
| 264 | * register information for crash reporting. |
| 265 | * It needs to return with x6 pointing to |
| 266 | * a list of register names in ascii and |
| 267 | * x8 - x15 having values of registers to be |
| 268 | * reported. |
| 269 | * --------------------------------------------- |
| 270 | */ |
| 271 | .section .rodata.cortex_a53_regs, "aS" |
| 272 | cortex_a53_regs: /* The ascii list of register names to be reported */ |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 273 | .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \ |
| 274 | "cpuactlr_el1", "" |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 275 | |
| 276 | func cortex_a53_cpu_reg_dump |
| 277 | adr x6, cortex_a53_regs |
| 278 | mrs x8, CPUECTLR_EL1 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 279 | mrs x9, CPUMERRSR_EL1 |
| 280 | mrs x10, L2MERRSR_EL1 |
Andre Przywara | 00eefd9 | 2016-10-06 16:54:53 +0100 | [diff] [blame] | 281 | mrs x11, CPUACTLR_EL1 |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 282 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 283 | endfunc cortex_a53_cpu_reg_dump |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 284 | |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 285 | declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ |
| 286 | cortex_a53_reset_func, \ |
| 287 | cortex_a53_core_pwr_dwn, \ |
| 288 | cortex_a53_cluster_pwr_dwn |