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git01.mediatek.com / filogic / atf / 361c1b36ee0efbd191bb113de4e38fd757a4cee4 / . / fdts / fvp-base-gicv3-psci-aarch32-common.dtsi
blob: a28a4a537292cdd1c98ff9ed051527c44d00014d [file] [log] [blame]
Imre Kisfe7c6c12019-08-08 19:06:12 +0200[diff] [blame]1/*
Balint Dobszay5ce2c322020-01-10 17:16:27 +0100[diff] [blame]2 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
Imre Kisfe7c6c12019-08-08 19:06:12 +0200[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/memreserve/ 0x80000000 0x00010000;
8
9/ {
10};
11
12/ {
13 model = "FVP Base";
14 compatible = "arm,vfp-base", "arm,vexpress";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 chosen { };
20
21 aliases {
22 serial0 = &v2m_serial0;
23 serial1 = &v2m_serial1;
24 serial2 = &v2m_serial2;
25 serial3 = &v2m_serial3;
26 };
27
28 psci {
29 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
30 method = "smc";
31 cpu_suspend = <0x84000001>;
32 cpu_off = <0x84000002>;
33 cpu_on = <0x84000003>;
34 sys_poweroff = <0x84000008>;
35 sys_reset = <0x84000009>;
Madhukar Pappireddy26b945c2019-12-27 12:02:34 -0600[diff] [blame]36 max-pwr-lvl = <2>;
Imre Kisfe7c6c12019-08-08 19:06:12 +0200[diff] [blame]37 };
38
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 cpu-map {
44 cluster0 {
45 core0 {
46 cpu = <&CPU0>;
47 };
48 core1 {
49 cpu = <&CPU1>;
50 };
51 core2 {
52 cpu = <&CPU2>;
53 };
54 core3 {
55 cpu = <&CPU3>;
56 };
57 };
58
59 cluster1 {
60 core0 {
61 cpu = <&CPU4>;
62 };
63 core1 {
64 cpu = <&CPU5>;
65 };
66 core2 {
67 cpu = <&CPU6>;
68 };
69 core3 {
70 cpu = <&CPU7>;
71 };
72 };
73 };
74
75 idle-states {
76 entry-method = "arm,psci";
77
78 CPU_SLEEP_0: cpu-sleep-0 {
79 compatible = "arm,idle-state";
80 local-timer-stop;
81 arm,psci-suspend-param = <0x0010000>;
82 entry-latency-us = <40>;
83 exit-latency-us = <100>;
84 min-residency-us = <150>;
85 };
86
87 CLUSTER_SLEEP_0: cluster-sleep-0 {
88 compatible = "arm,idle-state";
89 local-timer-stop;
90 arm,psci-suspend-param = <0x1010000>;
91 entry-latency-us = <500>;
92 exit-latency-us = <1000>;
93 min-residency-us = <2500>;
94 };
95 };
96
97 CPU0:cpu@0 {
98 device_type = "cpu";
99 compatible = "arm,armv8";
100 reg = <0x0>;
101 enable-method = "psci";
102 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
103 next-level-cache = <&L2_0>;
104 };
105
106 CPU1:cpu@1 {
107 device_type = "cpu";
108 compatible = "arm,armv8";
109 reg = <0x1>;
110 enable-method = "psci";
111 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
112 next-level-cache = <&L2_0>;
113 };
114
115 CPU2:cpu@2 {
116 device_type = "cpu";
117 compatible = "arm,armv8";
118 reg = <0x2>;
119 enable-method = "psci";
120 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
121 next-level-cache = <&L2_0>;
122 };
123
124 CPU3:cpu@3 {
125 device_type = "cpu";
126 compatible = "arm,armv8";
127 reg = <0x3>;
128 enable-method = "psci";
129 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
130 next-level-cache = <&L2_0>;
131 };
132
133 CPU4:cpu@100 {
134 device_type = "cpu";
135 compatible = "arm,armv8";
136 reg = <0x100>;
137 enable-method = "psci";
138 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
139 next-level-cache = <&L2_0>;
140 };
141
142 CPU5:cpu@101 {
143 device_type = "cpu";
144 compatible = "arm,armv8";
145 reg = <0x101>;
146 enable-method = "psci";
147 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
148 next-level-cache = <&L2_0>;
149 };
150
151 CPU6:cpu@102 {
152 device_type = "cpu";
153 compatible = "arm,armv8";
154 reg = <0x102>;
155 enable-method = "psci";
156 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
157 next-level-cache = <&L2_0>;
158 };
159
160 CPU7:cpu@103 {
161 device_type = "cpu";
162 compatible = "arm,armv8";
163 reg = <0x103>;
164 enable-method = "psci";
165 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
166 next-level-cache = <&L2_0>;
167 };
168
169 L2_0: l2-cache0 {
170 compatible = "cache";
171 };
172 };
173
174 memory@80000000 {
175 device_type = "memory";
176 reg = <0x00000000 0x80000000 0 0x7F000000>,
177 <0x00000008 0x80000000 0 0x80000000>;
178 };
179
180 gic: interrupt-controller@2f000000 {
181 compatible = "arm,gic-v3";
182 #interrupt-cells = <3>;
183 #address-cells = <2>;
184 #size-cells = <2>;
185 ranges;
186 interrupt-controller;
187 reg = <0x0 0x2f000000 0 0x10000>, // GICD
188 <0x0 0x2f100000 0 0x200000>, // GICR
189 <0x0 0x2c000000 0 0x2000>, // GICC
190 <0x0 0x2c010000 0 0x2000>, // GICH
191 <0x0 0x2c02f000 0 0x2000>; // GICV
192 interrupts = <1 9 4>;
193
194 its: its@2f020000 {
195 compatible = "arm,gic-v3-its";
196 msi-controller;
197 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
198 };
199 };
200
201 timer {
202 compatible = "arm,armv8-timer";
203 interrupts = <1 13 0xff01>,
204 <1 14 0xff01>,
205 <1 11 0xff01>,
206 <1 10 0xff01>;
207 clock-frequency = <100000000>;
208 };
209
210 timer@2a810000 {
211 compatible = "arm,armv7-timer-mem";
212 reg = <0x0 0x2a810000 0x0 0x10000>;
213 clock-frequency = <100000000>;
214 #address-cells = <2>;
215 #size-cells = <2>;
216 ranges;
217 frame@2a830000 {
218 frame-number = <1>;
219 interrupts = <0 26 4>;
220 reg = <0x0 0x2a830000 0x0 0x10000>;
221 };
222 };
223
224 pmu {
225 compatible = "arm,armv8-pmuv3";
226 interrupts = <0 60 4>,
227 <0 61 4>,
228 <0 62 4>,
229 <0 63 4>;
230 };
231
232 smb {
233 compatible = "simple-bus";
234
235 #address-cells = <2>;
236 #size-cells = <1>;
237 ranges = <0 0 0 0x08000000 0x04000000>,
238 <1 0 0 0x14000000 0x04000000>,
239 <2 0 0 0x18000000 0x04000000>,
240 <3 0 0 0x1c000000 0x04000000>,
241 <4 0 0 0x0c000000 0x04000000>,
242 <5 0 0 0x10000000 0x04000000>;
243
244 #interrupt-cells = <1>;
245 interrupt-map-mask = <0 0 63>;
246 interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
247 <0 0 1 &gic 0 0 0 1 4>,
248 <0 0 2 &gic 0 0 0 2 4>,
249 <0 0 3 &gic 0 0 0 3 4>,
250 <0 0 4 &gic 0 0 0 4 4>,
251 <0 0 5 &gic 0 0 0 5 4>,
252 <0 0 6 &gic 0 0 0 6 4>,
253 <0 0 7 &gic 0 0 0 7 4>,
254 <0 0 8 &gic 0 0 0 8 4>,
255 <0 0 9 &gic 0 0 0 9 4>,
256 <0 0 10 &gic 0 0 0 10 4>,
257 <0 0 11 &gic 0 0 0 11 4>,
258 <0 0 12 &gic 0 0 0 12 4>,
259 <0 0 13 &gic 0 0 0 13 4>,
260 <0 0 14 &gic 0 0 0 14 4>,
261 <0 0 15 &gic 0 0 0 15 4>,
262 <0 0 16 &gic 0 0 0 16 4>,
263 <0 0 17 &gic 0 0 0 17 4>,
264 <0 0 18 &gic 0 0 0 18 4>,
265 <0 0 19 &gic 0 0 0 19 4>,
266 <0 0 20 &gic 0 0 0 20 4>,
267 <0 0 21 &gic 0 0 0 21 4>,
268 <0 0 22 &gic 0 0 0 22 4>,
269 <0 0 23 &gic 0 0 0 23 4>,
270 <0 0 24 &gic 0 0 0 24 4>,
271 <0 0 25 &gic 0 0 0 25 4>,
272 <0 0 26 &gic 0 0 0 26 4>,
273 <0 0 27 &gic 0 0 0 27 4>,
274 <0 0 28 &gic 0 0 0 28 4>,
275 <0 0 29 &gic 0 0 0 29 4>,
276 <0 0 30 &gic 0 0 0 30 4>,
277 <0 0 31 &gic 0 0 0 31 4>,
278 <0 0 32 &gic 0 0 0 32 4>,
279 <0 0 33 &gic 0 0 0 33 4>,
280 <0 0 34 &gic 0 0 0 34 4>,
281 <0 0 35 &gic 0 0 0 35 4>,
282 <0 0 36 &gic 0 0 0 36 4>,
283 <0 0 37 &gic 0 0 0 37 4>,
284 <0 0 38 &gic 0 0 0 38 4>,
285 <0 0 39 &gic 0 0 0 39 4>,
286 <0 0 40 &gic 0 0 0 40 4>,
287 <0 0 41 &gic 0 0 0 41 4>,
288 <0 0 42 &gic 0 0 0 42 4>;
289
Balint Dobszay5ce2c322020-01-10 17:16:27 +0100[diff] [blame]290 #include "rtsm_ve-motherboard-aarch32.dtsi"
Imre Kisfe7c6c12019-08-08 19:06:12 +0200[diff] [blame]291 };
292
293 panels {
294 panel@0 {
295 compatible = "panel";
296 mode = "XVGA";
297 refresh = <60>;
298 xres = <1024>;
299 yres = <768>;
300 pixclock = <15748>;
301 left_margin = <152>;
302 right_margin = <48>;
303 upper_margin = <23>;
304 lower_margin = <3>;
305 hsync_len = <104>;
306 vsync_len = <4>;
307 sync = <0>;
308 vmode = "FB_VMODE_NONINTERLACED";
309 tim2 = "TIM2_BCD", "TIM2_IPC";
310 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
311 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
312 bpp = <16>;
313 };
314 };
315};