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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Roberto Vargas2ca18d92018-02-12 12:36:17 +00002 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
9#include <common/debug.h>
10#include <drivers/arm/tzc400.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000011#include <plat/arm/common/plat_arm.h>
Dan Handley9df48042015-03-19 18:58:55 +000012
13/* Weak definitions may be overridden in specific ARM standard platform */
14#pragma weak plat_arm_security_setup
15
16
17/*******************************************************************************
18 * Initialize the TrustZone Controller for ARM standard platforms.
Sandrine Bailleux03897bb2015-11-26 16:31:34 +000019 * When booting an EL3 payload, this is simplified: we configure region 0 with
20 * secure access only and do not enable any other region.
Dan Handley9df48042015-03-19 18:58:55 +000021 ******************************************************************************/
Summer Qin5ce394c2018-03-12 11:28:26 +080022void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions)
Dan Handley9df48042015-03-19 18:58:55 +000023{
Summer Qin5ce394c2018-03-12 11:28:26 +080024#ifndef EL3_PAYLOAD_BASE
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010025 unsigned int region_index = 1U;
Summer Qin5ce394c2018-03-12 11:28:26 +080026 const arm_tzc_regions_info_t *p;
27 const arm_tzc_regions_info_t init_tzc_regions[] = {
28 ARM_TZC_REGIONS_DEF,
29 {0}
30 };
31#endif
32
Dan Handley9df48042015-03-19 18:58:55 +000033 INFO("Configuring TrustZone Controller\n");
34
Soby Mathew9c708b52016-02-26 14:23:19 +000035 tzc400_init(PLAT_ARM_TZC_BASE);
Dan Handley9df48042015-03-19 18:58:55 +000036
37 /* Disable filters. */
Soby Mathew9c708b52016-02-26 14:23:19 +000038 tzc400_disable_filters();
Dan Handley9df48042015-03-19 18:58:55 +000039
Sandrine Bailleux03897bb2015-11-26 16:31:34 +000040#ifndef EL3_PAYLOAD_BASE
Summer Qin5ce394c2018-03-12 11:28:26 +080041 if (tzc_regions == NULL)
42 p = init_tzc_regions;
43 else
44 p = tzc_regions;
Soby Mathew7e4d6652017-05-10 11:50:30 +010045
Dan Handley9df48042015-03-19 18:58:55 +000046 /* Region 0 set to no access by default */
Soby Mathew9c708b52016-02-26 14:23:19 +000047 tzc400_configure_region0(TZC_REGION_S_NONE, 0);
Dan Handley9df48042015-03-19 18:58:55 +000048
Summer Qin5ce394c2018-03-12 11:28:26 +080049 /* Rest Regions set according to tzc_regions array */
50 for (; p->base != 0ULL; p++) {
51 tzc400_configure_region(PLAT_ARM_TZC_FILTERS, region_index,
52 p->base, p->end, p->sec_attr, p->nsaid_permissions);
53 region_index++;
54 }
Dan Handley9df48042015-03-19 18:58:55 +000055
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010056 INFO("Total %u regions set.\n", region_index);
Antonio Nino Diaz7289f922017-11-09 11:34:09 +000057
58#else /* if defined(EL3_PAYLOAD_BASE) */
59
Soby Mathew15b149e2017-11-13 08:29:45 +000060 /* Allow Secure and Non-secure access to DRAM for EL3 payloads */
61 tzc400_configure_region0(TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS);
Antonio Nino Diaz7289f922017-11-09 11:34:09 +000062
Sandrine Bailleux03897bb2015-11-26 16:31:34 +000063#endif /* EL3_PAYLOAD_BASE */
Dan Handley9df48042015-03-19 18:58:55 +000064
65 /*
66 * Raise an exception if a NS device tries to access secure memory
67 * TODO: Add interrupt handling support.
68 */
Soby Mathew9c708b52016-02-26 14:23:19 +000069 tzc400_set_action(TZC_ACTION_ERR);
Dan Handley9df48042015-03-19 18:58:55 +000070
71 /* Enable filters. */
Soby Mathew9c708b52016-02-26 14:23:19 +000072 tzc400_enable_filters();
Dan Handley9df48042015-03-19 18:58:55 +000073}
74
75void plat_arm_security_setup(void)
76{
Summer Qin5ce394c2018-03-12 11:28:26 +080077 arm_tzc400_setup(NULL);
Dan Handley9df48042015-03-19 18:58:55 +000078}