| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __TEGRA_DEF_H__ |
| 32 | #define __TEGRA_DEF_H__ |
| 33 | |
| 34 | #include <platform_def.h> |
| 35 | |
| 36 | /******************************************************************************* |
| Varun Wadekar | 81b1383 | 2015-07-03 16:31:28 +0530 | [diff] [blame] | 37 | * Power down state IDs |
| 38 | ******************************************************************************/ |
| 39 | #define PSTATE_ID_CORE_POWERDN 7 |
| 40 | #define PSTATE_ID_CLUSTER_IDLE 16 |
| 41 | #define PSTATE_ID_CLUSTER_POWERDN 17 |
| 42 | #define PSTATE_ID_SOC_POWERDN 27 |
| 43 | |
| 44 | /******************************************************************************* |
| 45 | * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` |
| 46 | * call as the `state-id` field in the 'power state' parameter. |
| 47 | ******************************************************************************/ |
| 48 | #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN |
| 49 | |
| 50 | /******************************************************************************* |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 51 | * Implementation defined ACTLR_EL3 bit definitions |
| 52 | ******************************************************************************/ |
| 53 | #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) |
| 54 | #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) |
| 55 | #define ACTLR_EL3_L2CTLR_BIT (1 << 4) |
| 56 | #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) |
| 57 | #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) |
| 58 | #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ |
| 59 | ACTLR_EL3_L2ECTLR_BIT | \ |
| 60 | ACTLR_EL3_L2CTLR_BIT | \ |
| 61 | ACTLR_EL3_CPUECTLR_BIT | \ |
| 62 | ACTLR_EL3_CPUACTLR_BIT) |
| 63 | |
| 64 | /******************************************************************************* |
| 65 | * GIC memory map |
| 66 | ******************************************************************************/ |
| 67 | #define TEGRA_GICD_BASE 0x50041000 |
| 68 | #define TEGRA_GICC_BASE 0x50042000 |
| 69 | |
| 70 | /******************************************************************************* |
| 71 | * Tegra micro-seconds timer constants |
| 72 | ******************************************************************************/ |
| 73 | #define TEGRA_TMRUS_BASE 0x60005010 |
| 74 | |
| 75 | /******************************************************************************* |
| 76 | * Tegra Clock and Reset Controller constants |
| 77 | ******************************************************************************/ |
| 78 | #define TEGRA_CAR_RESET_BASE 0x60006000 |
| 79 | |
| 80 | /******************************************************************************* |
| 81 | * Tegra Flow Controller constants |
| 82 | ******************************************************************************/ |
| 83 | #define TEGRA_FLOWCTRL_BASE 0x60007000 |
| 84 | |
| 85 | /******************************************************************************* |
| 86 | * Tegra Secure Boot Controller constants |
| 87 | ******************************************************************************/ |
| 88 | #define TEGRA_SB_BASE 0x6000C200 |
| 89 | |
| 90 | /******************************************************************************* |
| 91 | * Tegra Exception Vectors constants |
| 92 | ******************************************************************************/ |
| 93 | #define TEGRA_EVP_BASE 0x6000F000 |
| 94 | |
| 95 | /******************************************************************************* |
| 96 | * Tegra Power Mgmt Controller constants |
| 97 | ******************************************************************************/ |
| 98 | #define TEGRA_PMC_BASE 0x7000E400 |
| 99 | |
| 100 | /******************************************************************************* |
| 101 | * Tegra Memory Controller constants |
| 102 | ******************************************************************************/ |
| 103 | #define TEGRA_MC_BASE 0x70019000 |
| 104 | |
| 105 | #endif /* __TEGRA_DEF_H__ */ |