blob: b4dab085ec0c23c42a1fd556dd0c2b5fdb9815c4 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Anthony Steinhauser0f7e6012020-01-07 15:44:06 -08002 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00006#ifndef ASM_MACROS_S
7#define ASM_MACROS_S
Achin Gupta4f6ad662013-10-25 09:08:21 +01008
Dan Handley2bd4ef22014-04-09 13:14:54 +01009#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/asm_macros_common.S>
11#include <lib/spinlock.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010012
Jeenu Viswambharan58e81482018-04-27 15:06:57 +010013/*
14 * TLBI instruction with type specifier that implements the workaround for
Soby Mathew16d006b2019-05-03 13:17:56 +010015 * errata 813419 of Cortex-A57 or errata 1286807 of Cortex-A76.
Jeenu Viswambharan58e81482018-04-27 15:06:57 +010016 */
Soby Mathew16d006b2019-05-03 13:17:56 +010017#if ERRATA_A57_813419 || ERRATA_A76_1286807
Jeenu Viswambharan58e81482018-04-27 15:06:57 +010018#define TLB_INVALIDATE(_type) \
19 tlbi _type; \
20 dsb ish; \
21 tlbi _type
22#else
23#define TLB_INVALIDATE(_type) \
24 tlbi _type
25#endif
26
Dan Handley2bd4ef22014-04-09 13:14:54 +010027
Achin Gupta4f6ad662013-10-25 09:08:21 +010028 .macro func_prologue
29 stp x29, x30, [sp, #-0x10]!
30 mov x29,sp
31 .endm
32
33 .macro func_epilogue
34 ldp x29, x30, [sp], #0x10
35 .endm
36
37
38 .macro dcache_line_size reg, tmp
Achin Gupta07f4e072014-02-02 12:02:23 +000039 mrs \tmp, ctr_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +010040 ubfx \tmp, \tmp, #16, #4
Achin Gupta07f4e072014-02-02 12:02:23 +000041 mov \reg, #4
42 lsl \reg, \reg, \tmp
Achin Gupta4f6ad662013-10-25 09:08:21 +010043 .endm
44
45
46 .macro icache_line_size reg, tmp
Achin Gupta07f4e072014-02-02 12:02:23 +000047 mrs \tmp, ctr_el0
48 and \tmp, \tmp, #0xf
49 mov \reg, #4
50 lsl \reg, \reg, \tmp
Achin Gupta4f6ad662013-10-25 09:08:21 +010051 .endm
52
53
Achin Gupta4f6ad662013-10-25 09:08:21 +010054 .macro smc_check label
Andrew Thoelkef977ed82014-04-28 12:32:02 +010055 mrs x0, esr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010056 ubfx x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
57 cmp x0, #EC_AARCH64_SMC
58 b.ne $label
59 .endm
60
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010061 /*
62 * Declare the exception vector table, enforcing it is aligned on a
63 * 2KB boundary, as required by the ARMv8 architecture.
Sandrine Bailleux618ba992016-05-24 16:22:59 +010064 * Use zero bytes as the fill value to be stored in the padding bytes
65 * so that it inserts illegal AArch64 instructions. This increases
66 * security, robustness and potentially facilitates debugging.
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010067 */
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010068 .macro vector_base label, section_name=.vectors
69 .section \section_name, "ax"
Sandrine Bailleux618ba992016-05-24 16:22:59 +010070 .align 11, 0
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010071 \label:
72 .endm
73
74 /*
75 * Create an entry in the exception vector table, enforcing it is
76 * aligned on a 128-byte boundary, as required by the ARMv8 architecture.
Sandrine Bailleux618ba992016-05-24 16:22:59 +010077 * Use zero bytes as the fill value to be stored in the padding bytes
78 * so that it inserts illegal AArch64 instructions. This increases
79 * security, robustness and potentially facilitates debugging.
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010080 */
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010081 .macro vector_entry label, section_name=.vectors
Douglas Raillardefa50b52017-08-07 16:20:46 +010082 .cfi_sections .debug_frame
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010083 .section \section_name, "ax"
Sandrine Bailleux618ba992016-05-24 16:22:59 +010084 .align 7, 0
Douglas Raillardefa50b52017-08-07 16:20:46 +010085 .type \label, %function
Douglas Raillardefa50b52017-08-07 16:20:46 +010086 .cfi_startproc
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010087 \label:
88 .endm
Achin Gupta4f6ad662013-10-25 09:08:21 +010089
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000090 /*
Roberto Vargas95f30ab2018-04-17 11:31:43 +010091 * Add the bytes until fill the full exception vector, whose size is always
92 * 32 instructions. If there are more than 32 instructions in the
93 * exception vector then an error is emitted.
94 */
95 .macro end_vector_entry label
96 .cfi_endproc
97 .fill \label + (32 * 4) - .
98 .endm
99
100 /*
Soby Mathewb0082d22015-04-09 13:40:55 +0100101 * This macro calculates the base address of the current CPU's MP stack
102 * using the plat_my_core_pos() index, the name of the stack storage
103 * and the size of each stack
104 * Out: X0 = physical address of stack base
105 * Clobber: X30, X1, X2
106 */
107 .macro get_my_mp_stack _name, _size
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100108 bl plat_my_core_pos
109 adrp x2, (\_name + \_size)
110 add x2, x2, :lo12:(\_name + \_size)
Soby Mathewb0082d22015-04-09 13:40:55 +0100111 mov x1, #\_size
112 madd x0, x0, x1, x2
113 .endm
114
115 /*
Andrew Thoelke65668f92014-03-20 10:48:23 +0000116 * This macro calculates the base address of a UP stack using the
117 * name of the stack storage and the size of the stack
118 * Out: X0 = physical address of stack base
119 */
120 .macro get_up_stack _name, _size
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100121 adrp x0, (\_name + \_size)
122 add x0, x0, :lo12:(\_name + \_size)
Andrew Thoelke65668f92014-03-20 10:48:23 +0000123 .endm
Soby Mathew066f7132014-07-14 16:57:23 +0100124
125 /*
126 * Helper macro to generate the best mov/movk combinations according
127 * the value to be moved. The 16 bits from '_shift' are tested and
128 * if not zero, they are moved into '_reg' without affecting
129 * other bits.
130 */
131 .macro _mov_imm16 _reg, _val, _shift
132 .if (\_val >> \_shift) & 0xffff
133 .if (\_val & (1 << \_shift - 1))
134 movk \_reg, (\_val >> \_shift) & 0xffff, LSL \_shift
135 .else
136 mov \_reg, \_val & (0xffff << \_shift)
137 .endif
138 .endif
139 .endm
140
141 /*
142 * Helper macro to load arbitrary values into 32 or 64-bit registers
143 * which generates the best mov/movk combinations. Many base addresses
144 * are 64KB aligned the macro will eliminate updating bits 15:0 in
145 * that case
146 */
147 .macro mov_imm _reg, _val
148 .if (\_val) == 0
149 mov \_reg, #0
150 .else
151 _mov_imm16 \_reg, (\_val), 0
152 _mov_imm16 \_reg, (\_val), 16
153 _mov_imm16 \_reg, (\_val), 32
154 _mov_imm16 \_reg, (\_val), 48
155 .endif
156 .endm
Dan Handleyea596682015-04-01 17:34:24 +0100157
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000158 /*
159 * Macro to mark instances where we're jumping to a function and don't
160 * expect a return. To provide the function being jumped to with
161 * additional information, we use 'bl' instruction to jump rather than
162 * 'b'.
163 *
164 * Debuggers infer the location of a call from where LR points to, which
165 * is usually the instruction after 'bl'. If this macro expansion
166 * happens to be the last location in a function, that'll cause the LR
167 * to point a location beyond the function, thereby misleading debugger
168 * back trace. We therefore insert a 'nop' after the function call for
169 * debug builds, unless 'skip_nop' parameter is non-zero.
170 */
171 .macro no_ret _func:req, skip_nop=0
172 bl \_func
173#if DEBUG
174 .ifeq \skip_nop
175 nop
176 .endif
177#endif
178 .endm
179
Jeenu Viswambharan54ec86a2017-01-19 14:23:36 +0000180 /*
181 * Reserve space for a spin lock in assembly file.
182 */
183 .macro define_asm_spinlock _name:req
184 .align SPINLOCK_ASM_ALIGN
185 \_name:
186 .space SPINLOCK_ASM_SIZE
187 .endm
188
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100189#if RAS_EXTENSION
190 .macro esb
191 .inst 0xd503221f
192 .endm
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100193#endif
194
195 /*
196 * Helper macro to read system register value into x0
197 */
198 .macro read reg:req
199#if ENABLE_BTI
200 bti j
201#endif
202 mrs x0, \reg
203 ret
204 .endm
205
206 /*
207 * Helper macro to write value from x1 to system register
208 */
209 .macro write reg:req
210#if ENABLE_BTI
211 bti j
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100212#endif
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100213 msr \reg, x1
214 ret
215 .endm
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100216
Anthony Steinhauser0f7e6012020-01-07 15:44:06 -0800217 /*
Andre Przywarac735f1c2022-11-25 14:10:13 +0000218 * The "sb" instruction was introduced later into the architecture,
219 * so not all toolchains understand it. Some deny its usage unless
220 * a supported processor is specified on the build command line.
221 * Use sb's system register encoding to work around this, we already
222 * guard the sb execution with a feature flag.
223 */
224
225 .macro sb_barrier_insn
226 msr SYSREG_SB, xzr
227 .endm
228
229 /*
Bipin Ravi9ee6dd42022-10-13 17:25:51 -0500230 * Macro for using speculation barrier instruction introduced by
231 * FEAT_SB, if it's enabled.
232 */
233 .macro speculation_barrier
234#if ENABLE_FEAT_SB
Andre Przywarac735f1c2022-11-25 14:10:13 +0000235 sb_barrier_insn
Bipin Ravi9ee6dd42022-10-13 17:25:51 -0500236#else
237 dsb sy
238 isb
239#endif
240 .endm
241
242 /*
Chris Kay08fec332021-03-09 13:34:35 +0000243 * Macro for mitigating against speculative execution beyond ERET. Uses the
244 * speculation barrier instruction introduced by FEAT_SB, if it's enabled.
Anthony Steinhauser0f7e6012020-01-07 15:44:06 -0800245 */
246 .macro exception_return
247 eret
Chris Kay08fec332021-03-09 13:34:35 +0000248#if ENABLE_FEAT_SB
Andre Przywarac735f1c2022-11-25 14:10:13 +0000249 sb_barrier_insn
Madhukar Pappireddybfe7bb62020-03-10 18:04:59 -0500250#else
251 dsb nsh
Anthony Steinhauser0f7e6012020-01-07 15:44:06 -0800252 isb
Madhukar Pappireddybfe7bb62020-03-10 18:04:59 -0500253#endif
Anthony Steinhauser0f7e6012020-01-07 15:44:06 -0800254 .endm
255
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000256#endif /* ASM_MACROS_S */