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Usama Arifbec5afd2020-04-17 16:13:39 +01001/*
Usama Arifa49bd492021-08-17 17:57:10 +01002 * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
Usama Arifbec5afd2020-04-17 16:13:39 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8
9#include <platform_def.h>
10
11#include <plat/common/platform.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
14#include <drivers/arm/ccn.h>
15#include <plat/arm/common/plat_arm.h>
16#include <plat/common/platform.h>
17#include <drivers/arm/sbsa.h>
Olivier Deprez21cf3602020-07-30 17:18:33 +020018
19#if SPM_MM
Usama Arifbec5afd2020-04-17 16:13:39 +010020#include <services/spm_mm_partition.h>
Olivier Deprez21cf3602020-07-30 17:18:33 +020021#endif
Usama Arifbec5afd2020-04-17 16:13:39 +010022
23/*
24 * Table of regions for different BL stages to map using the MMU.
25 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
26 * arm_configure_mmu_elx() will give the available subset of that.
27 */
28#if IMAGE_BL1
29const mmap_region_t plat_arm_mmap[] = {
30 ARM_MAP_SHARED_RAM,
Usama Ariff1513622021-04-09 17:07:41 +010031 TC_FLASH0_RO,
32 TC_MAP_DEVICE,
Usama Arifbec5afd2020-04-17 16:13:39 +010033 {0}
34};
35#endif
36#if IMAGE_BL2
37const mmap_region_t plat_arm_mmap[] = {
38 ARM_MAP_SHARED_RAM,
Usama Ariff1513622021-04-09 17:07:41 +010039 TC_FLASH0_RO,
40 TC_MAP_DEVICE,
41 TC_MAP_NS_DRAM1,
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +010042#if defined(SPD_spmd)
Usama Ariff1513622021-04-09 17:07:41 +010043 TC_MAP_TZC_DRAM1,
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +010044#endif
Usama Arifbec5afd2020-04-17 16:13:39 +010045#if ARM_BL31_IN_DRAM
46 ARM_MAP_BL31_SEC_DRAM,
47#endif
48#if SPM_MM
49 ARM_SP_IMAGE_MMAP,
50#endif
51#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
52 ARM_MAP_BL1_RW,
53#endif
Arunachalam Ganapathy29786f72020-11-17 14:48:59 +000054#ifdef SPD_opteed
55 ARM_MAP_OPTEE_CORE_MEM,
56 ARM_OPTEE_PAGEABLE_LOAD_MEM,
57#endif
Usama Arifbec5afd2020-04-17 16:13:39 +010058 {0}
59};
60#endif
61#if IMAGE_BL31
62const mmap_region_t plat_arm_mmap[] = {
63 ARM_MAP_SHARED_RAM,
64 V2M_MAP_IOFPGA,
Usama Ariff1513622021-04-09 17:07:41 +010065 TC_MAP_DEVICE,
Usama Arifa49bd492021-08-17 17:57:10 +010066 PLAT_DTB_DRAM_NS,
Usama Arifbec5afd2020-04-17 16:13:39 +010067#if SPM_MM
68 ARM_SPM_BUF_EL3_MMAP,
69#endif
70 {0}
71};
72
73#if SPM_MM && defined(IMAGE_BL31)
74const mmap_region_t plat_arm_secure_partition_mmap[] = {
75 PLAT_ARM_SECURE_MAP_DEVICE,
76 ARM_SP_IMAGE_MMAP,
77 ARM_SP_IMAGE_NS_BUF_MMAP,
78 ARM_SP_CPER_BUF_MMAP,
79 ARM_SP_IMAGE_RW_MMAP,
80 ARM_SPM_BUF_EL0_MMAP,
81 {0}
82};
83#endif /* SPM_MM && defined(IMAGE_BL31) */
84#endif
85
86ARM_CASSERT_MMAP
87
88#if SPM_MM && defined(IMAGE_BL31)
89/*
90 * Boot information passed to a secure partition during initialisation. Linear
91 * indices in MP information will be filled at runtime.
92 */
93static spm_mm_mp_info_t sp_mp_info[] = {
94 [0] = {0x81000000, 0},
95 [1] = {0x81000100, 0},
96 [2] = {0x81000200, 0},
97 [3] = {0x81000300, 0},
98 [4] = {0x81010000, 0},
99 [5] = {0x81010100, 0},
100 [6] = {0x81010200, 0},
101 [7] = {0x81010300, 0},
102};
103
104const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
105 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
106 .h.version = VERSION_1,
107 .h.size = sizeof(spm_mm_boot_info_t),
108 .h.attr = 0,
109 .sp_mem_base = ARM_SP_IMAGE_BASE,
110 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
111 .sp_image_base = ARM_SP_IMAGE_BASE,
112 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
113 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
114 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
115 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
116 .sp_image_size = ARM_SP_IMAGE_SIZE,
117 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
118 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
119 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
120 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
121 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
122 .num_cpus = PLATFORM_CORE_COUNT,
123 .mp_info = &sp_mp_info[0],
124};
125
126const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
127{
128 return plat_arm_secure_partition_mmap;
129}
130
131const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
132 void *cookie)
133{
134 return &plat_arm_secure_partition_boot_info;
135}
136#endif /* SPM_MM && defined(IMAGE_BL31) */
137
138#if TRUSTED_BOARD_BOOT
139int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
140{
141 assert(heap_addr != NULL);
142 assert(heap_size != NULL);
143
144 return arm_get_mbedtls_heap(heap_addr, heap_size);
145}
146#endif
147
148void plat_arm_secure_wdt_start(void)
149{
150 sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
151}
152
153void plat_arm_secure_wdt_stop(void)
154{
155 sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
156}