Vikram Kanigiri | 510d87b | 2016-01-29 12:32:58 +0000 | [diff] [blame] | 1 | /* |
Summer Qin | 5ce394c | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 2 | * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. |
Vikram Kanigiri | 510d87b | 2016-01-29 12:32:58 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Vikram Kanigiri | 510d87b | 2016-01-29 12:32:58 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arm_def.h> |
| 8 | #include <assert.h> |
| 9 | #include <debug.h> |
Nariman Poushin | 8b8df93 | 2018-04-27 18:49:52 +0100 | [diff] [blame] | 10 | #include <plat_arm.h> |
Vikram Kanigiri | 510d87b | 2016-01-29 12:32:58 +0000 | [diff] [blame] | 11 | #include <platform_def.h> |
| 12 | #include <tzc_dmc500.h> |
| 13 | |
| 14 | /******************************************************************************* |
| 15 | * Initialize the DMC500-TrustZone Controller for ARM standard platforms. |
Vikram Kanigiri | 510d87b | 2016-01-29 12:32:58 +0000 | [diff] [blame] | 16 | * When booting an EL3 payload, this is simplified: we configure region 0 with |
| 17 | * secure access only and do not enable any other region. |
| 18 | ******************************************************************************/ |
Summer Qin | 5ce394c | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 19 | void arm_tzc_dmc500_setup(tzc_dmc500_driver_data_t *plat_driver_data, |
| 20 | const arm_tzc_regions_info_t *tzc_regions) |
Vikram Kanigiri | 510d87b | 2016-01-29 12:32:58 +0000 | [diff] [blame] | 21 | { |
Summer Qin | 5ce394c | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 22 | #ifndef EL3_PAYLOAD_BASE |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 23 | unsigned int region_index = 1U; |
Summer Qin | 5ce394c | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 24 | const arm_tzc_regions_info_t *p; |
| 25 | const arm_tzc_regions_info_t init_tzc_regions[] = { |
| 26 | ARM_TZC_REGIONS_DEF, |
| 27 | {0} |
| 28 | }; |
| 29 | #endif |
| 30 | |
Vikram Kanigiri | 510d87b | 2016-01-29 12:32:58 +0000 | [diff] [blame] | 31 | assert(plat_driver_data); |
| 32 | |
| 33 | INFO("Configuring DMC-500 TZ Settings\n"); |
| 34 | |
| 35 | tzc_dmc500_driver_init(plat_driver_data); |
| 36 | |
| 37 | #ifndef EL3_PAYLOAD_BASE |
Summer Qin | 5ce394c | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 38 | if (tzc_regions == NULL) |
| 39 | p = init_tzc_regions; |
| 40 | else |
| 41 | p = tzc_regions; |
| 42 | |
Vikram Kanigiri | 510d87b | 2016-01-29 12:32:58 +0000 | [diff] [blame] | 43 | /* Region 0 set to no access by default */ |
| 44 | tzc_dmc500_configure_region0(TZC_REGION_S_NONE, 0); |
| 45 | |
Summer Qin | 5ce394c | 2018-03-12 11:28:26 +0800 | [diff] [blame] | 46 | /* Rest Regions set according to tzc_regions array */ |
| 47 | for (; p->base != 0ULL; p++) { |
| 48 | tzc_dmc500_configure_region(region_index, p->base, p->end, |
| 49 | p->sec_attr, p->nsaid_permissions); |
| 50 | region_index++; |
| 51 | } |
Vikram Kanigiri | 510d87b | 2016-01-29 12:32:58 +0000 | [diff] [blame] | 52 | |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 53 | INFO("Total %u regions set.\n", region_index); |
Vikram Kanigiri | 510d87b | 2016-01-29 12:32:58 +0000 | [diff] [blame] | 54 | |
Vikram Kanigiri | 510d87b | 2016-01-29 12:32:58 +0000 | [diff] [blame] | 55 | #else |
| 56 | /* Allow secure access only to DRAM for EL3 payloads */ |
| 57 | tzc_dmc500_configure_region0(TZC_REGION_S_RDWR, 0); |
| 58 | #endif |
| 59 | /* |
| 60 | * Raise an exception if a NS device tries to access secure memory |
| 61 | * TODO: Add interrupt handling support. |
| 62 | */ |
| 63 | tzc_dmc500_set_action(TZC_ACTION_RV_LOWERR); |
| 64 | |
| 65 | /* |
| 66 | * Flush the configuration settings to have an affect. Validate |
| 67 | * flush by checking FILTER_EN is set on region 1 attributes |
| 68 | * register. |
| 69 | */ |
| 70 | tzc_dmc500_config_complete(); |
| 71 | |
| 72 | /* |
| 73 | * Wait for the flush to complete. |
| 74 | * TODO: Have a timeout for this loop |
| 75 | */ |
| 76 | while (tzc_dmc500_verify_complete()) |
| 77 | ; |
| 78 | } |