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Jayanth Dodderi Chidanand37de9162021-12-07 17:20:10 +00001/*
Arvind Ram Prakash5a03ddf2023-07-25 14:33:12 -05002 * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
Jayanth Dodderi Chidanand37de9162021-12-07 17:20:10 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <neoverse_poseidon.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
Bipin Ravi32464ba2022-05-06 16:02:30 -050013#include "wa_cve_2022_23960_bhb_vector.S"
Jayanth Dodderi Chidanand37de9162021-12-07 17:20:10 +000014
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "Neoverse Poseidon must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20/* 64-bit only core */
21#if CTX_INCLUDE_AARCH32_REGS == 1
22#error "Neoverse Poseidon supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
23#endif
24
Bipin Ravi32464ba2022-05-06 16:02:30 -050025#if WORKAROUND_CVE_2022_23960
26 wa_cve_2022_23960_bhb_vector_table NEOVERSE_POSEIDON_BHB_LOOP_COUNT, neoverse_poseidon
27#endif /* WORKAROUND_CVE_2022_23960 */
28
Arvind Ram Prakash5a03ddf2023-07-25 14:33:12 -050029workaround_reset_start neoverse_poseidon, CVE(2022,23960), WORKAROUND_CVE_2022_23960
30#if IMAGE_BL31
31 /*
32 * The Neoverse-poseidon generic vectors are overridden to apply errata
33 * mitigation on exception entry from lower ELs.
34 */
Arvind Ram Prakash34092e92023-07-25 14:42:46 -050035 override_vector_table wa_cve_vbar_neoverse_poseidon
36
Arvind Ram Prakash5a03ddf2023-07-25 14:33:12 -050037#endif /* IMAGE_BL31 */
38workaround_reset_end neoverse_poseidon, CVE(2022,23960)
39
40check_erratum_chosen neoverse_poseidon, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
41
Jayanth Dodderi Chidanand37de9162021-12-07 17:20:10 +000042 /* ---------------------------------------------
43 * HW will do the cache maintenance while powering down
44 * ---------------------------------------------
45 */
46func neoverse_poseidon_core_pwr_dwn
47 /* ---------------------------------------------
48 * Enable CPU power down bit in power control register
49 * ---------------------------------------------
50 */
Arvind Ram Prakash34092e92023-07-25 14:42:46 -050051 sysreg_bit_set NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, \
52 NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
53
Jayanth Dodderi Chidanand37de9162021-12-07 17:20:10 +000054 isb
55 ret
56endfunc neoverse_poseidon_core_pwr_dwn
57
Arvind Ram Prakash5a03ddf2023-07-25 14:33:12 -050058cpu_reset_func_start neoverse_poseidon
Jayanth Dodderi Chidanand37de9162021-12-07 17:20:10 +000059 /* Disable speculative loads */
60 msr SSBS, xzr
Arvind Ram Prakash5a03ddf2023-07-25 14:33:12 -050061cpu_reset_func_end neoverse_poseidon
Bipin Ravi32464ba2022-05-06 16:02:30 -050062
Arvind Ram Prakash5a03ddf2023-07-25 14:33:12 -050063errata_report_shim neoverse_poseidon
Bipin Ravi32464ba2022-05-06 16:02:30 -050064
Jayanth Dodderi Chidanand37de9162021-12-07 17:20:10 +000065 /* ---------------------------------------------
66 * This function provides Neoverse-Poseidon specific
67 * register information for crash reporting.
68 * It needs to return with x6 pointing to
69 * a list of register names in ascii and
70 * x8 - x15 having values of registers to be
71 * reported.
72 * ---------------------------------------------
73 */
74.section .rodata.neoverse_poseidon_regs, "aS"
75neoverse_poseidon_regs: /* The ascii list of register names to be reported */
76 .asciz "cpuectlr_el1", ""
77
78func neoverse_poseidon_cpu_reg_dump
79 adr x6, neoverse_poseidon_regs
80 mrs x8, NEOVERSE_POSEIDON_CPUECTLR_EL1
81 ret
82endfunc neoverse_poseidon_cpu_reg_dump
83
84declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_MIDR, \
85 neoverse_poseidon_reset_func, \
86 neoverse_poseidon_core_pwr_dwn