blob: 1cc0d5909137eeb67a009bed9fd543318c2f5222 [file] [log] [blame]
Jorge Ramirez-Ortiz1d753672018-09-23 09:41:53 +02001/*
2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9
10#define SCIF_INTERNAL_CLK 0
11#define SCIF_EXTARNAL_CLK 1
12#define SCIF_CLK SCIF_INTERNAL_CLK
13
14/* product register */
15#define PRR (0xFFF00044)
16#define PRR_PRODUCT_MASK (0x00007F00)
17#define PRR_CUT_MASK (0x000000FF)
18#define PRR_PRODUCT_H3_VER_10 (0x00004F00)
19#define PRR_PRODUCT_E3 (0x00005700)
20
21/* module stop */
22#define CPG_BASE (0xE6150000)
23#define CPG_SMSTPCR3 (0x013C)
24#define CPG_MSTPSR3 (0x0048)
25#define MSTP310 (1 << 10)
26#define CPG_CPGWPR (0x0900)
27
28/* scif */
29#define SCIF2_BASE (0xE6E88000)
30#define SCIF_SCSMR (0x00)
31#define SCIF_SCBRR (0x04)
32#define SCIF_SCSCR (0x08)
33#define SCIF_SCFTDR (0x0C)
34#define SCIF_SCFSR (0x10)
35#define SCIF_SCFRDR (0x14)
36#define SCIF_SCFCR (0x18)
37#define SCIF_SCFDR (0x1C)
38#define SCIF_SCSPTR (0x20)
39#define SCIF_SCLSR (0x24)
40#define SCIF_DL (0x30)
41#define SCIF_CKS (0x34)
42
43/* mode pin */
44#define RST_MODEMR (0xE6160060)
45#define MODEMR_MD12 (0x00001000)
46
47#define SCSMR_CA_MASK (1 << 7)
48#define SCSMR_CA_ASYNC (0x0000)
49#define SCSMR_CHR_MASK (1 << 6)
50#define SCSMR_CHR_8 (0x0000)
51#define SCSMR_PE_MASK (1 << 5)
52#define SCSMR_PE_DIS (0x0000)
53#define SCSMR_STOP_MASK (1 << 3)
54#define SCSMR_STOP_1 (0x0000)
55#define SCSMR_CKS_MASK (3 << 0)
56#define SCSMR_CKS_DIV1 (0x0000)
57#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + \
58 SCSMR_CHR_8 + \
59 SCSMR_PE_DIS + \
60 SCSMR_STOP_1 + \
61 SCSMR_CKS_DIV1)
62#define SCBRR_115200BPS (17)
63#define SCBRR_115200BPS_E3_SSCG (15)
64#define SCBRR_230400BPS (8)
65
66#define SCSCR_TE_MASK (1 << 5)
67#define SCSCR_TE_DIS (0x0000)
68#define SCSCR_TE_EN (0x0020)
69#define SCSCR_RE_MASK (1 << 4)
70#define SCSCR_RE_DIS (0x0000)
71#define SCSCR_RE_EN (0x0010)
72#define SCSCR_CKE_MASK (3 << 0)
73#define SCSCR_CKE_INT (0x0000)
74#define SCSCR_CKE_BRG (0x0002)
75#if SCIF_CLK == SCIF_EXTARNAL_CLK
76#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG)
77#else
78#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT)
79#endif
80#define SCFSR_INIT_DATA (0x0000)
81#define SCFCR_TTRG_MASK (3 << 4)
82#define SCFCR_TTRG_8 (0x0000)
83#define SCFCR_TTRG_0 (0x0030)
84#define SCFCR_TFRST_MASK (1 << 2)
85#define SCFCR_TFRST_DIS (0x0000)
86#define SCFCR_TFRST_EN (0x0004)
87#define SCFCR_RFRS_MASK (1 << 1)
88#define SCFCR_RFRS_DIS (0x0000)
89#define SCFCR_RFRS_EN (0x0002)
90#define SCFCR_INIT_DATA (SCFCR_TTRG_8)
91#define SCFDR_T_MASK (0x1f << 8)
92#define DL_INIT_DATA (8)
93#define CKS_CKS_DIV_MASK (1 << 15)
94#define CKS_CKS_DIV_CLK (0x0000)
95#define CKS_XIN_MASK (1 << 14)
96#define CKS_XIN_SCIF_CLK (0x0000)
97#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK)
98
99 .globl console_init
100 .globl console_uninit
101 .globl console_putc
102 .globl console_core_init
103 .globl console_core_putc
104 .globl console_getc
105 .globl console_flush
106
107 /*
108 * The console base is in the data section and not in .bss
109 * even though it is zero-init. In particular, this allows
110 * the console functions to start using this variable before
111 * the runtime memory is initialized for images which do not
112 * need to copy the .data section from ROM to RAM.
113 */
114 /* -----------------------------------------------
115 * int console_init(unsigned long base_addr,
116 * unsigned int uart_clk, unsigned int baud_rate)
117 * Function to initialize the console without a
118 * C Runtime to print debug information. It saves
119 * the console base to the data section.
120 * In: x0 - console base address
121 * w1 - Uart clock in Hz
122 * w2 - Baud rate
123 * out: return 1 on success.
124 * Clobber list : x1 - x3
125 * -----------------------------------------------
126 */
127func console_init
128 b console_core_init
129endfunc console_init
130
131func console_uninit
132 ret
133endfunc console_uninit
134
135 /* -----------------------------------------------
136 * int console_core_init(unsigned long base_addr,
137 * unsigned int uart_clk, unsigned int baud_rate)
138 * Function to initialize the console without a
139 * C Runtime to print debug information. This
140 * function will be accessed by console_init and
141 * crash reporting.
142 * In: x0 - console base address
143 * w1 - Uart clock in Hz
144 * w2 - Baud rate
145 * Out: return 1 on success
146 * Clobber list : x1, x2
147 * -----------------------------------------------
148 */
149func console_core_init
150 ldr x0, =CPG_BASE
151 ldr w1, [x0, #CPG_SMSTPCR3]
152 and w1, w1, #~MSTP310 /* MSTP310=0 */
153 mvn w2, w1
154 str w2, [x0, #CPG_CPGWPR]
155 str w1, [x0, #CPG_SMSTPCR3]
1565:
157 ldr w1, [x0, #CPG_MSTPSR3]
158 and w1, w1, #MSTP310
159 cbnz w1, 5b
160
161 ldr x0, =SCIF2_BASE
162 /* Clear bits TE and RE in SCSCR to 0 */
163 mov w1, #(SCSCR_TE_DIS + SCSCR_RE_DIS)
164 strh w1, [x0, #SCIF_SCSCR]
165 /* Set bits TFRST and RFRST in SCFCR to 1 */
166 ldrh w1, [x0, #SCIF_SCFCR]
167 orr w1, w1, #(SCFCR_TFRST_EN + SCFCR_RFRS_EN)
168 strh w1, [x0, #SCIF_SCFCR]
169 /* Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER
170 in SCLSR, then clear them to 0 */
171 mov w1, #SCFSR_INIT_DATA
172 strh w1, [x0, #SCIF_SCFSR]
173 mov w1, #0
174 strh w1, [x0, #SCIF_SCLSR]
175 /* Set bits CKE[1:0] in SCSCR */
176 ldrh w1, [x0, #SCIF_SCSCR]
177 and w1, w1, #~SCSCR_CKE_MASK
178 mov w2, #SCSCR_CKE_INT_CLK
179 orr w1, w1, w2
180 strh w1, [x0, #SCIF_SCSCR]
181 /* Set data transfer format in SCSMR */
182 mov w1, #SCSMR_INIT_DATA
183 strh w1, [x0, #SCIF_SCSMR]
184 /* Set value in SCBRR */
185#if SCIF_CLK == SCIF_INTERNAL_CLK
186 ldr x1, =PRR
187 ldr w1, [x1]
188 and w1, w1, #(PRR_PRODUCT_MASK | PRR_CUT_MASK)
189 mov w2, #PRR_PRODUCT_H3_VER_10
190 cmp w1, w2
191 beq 3f
192 and w1, w1, #PRR_PRODUCT_MASK
193 mov w2, #PRR_PRODUCT_E3
194 cmp w1, w2
195 bne 4f
196
197 ldr x1, =RST_MODEMR
198 ldr w1, [x1]
199 and w1, w1, #MODEMR_MD12
200 mov w2, #MODEMR_MD12
201 cmp w1, w2
202 bne 4f
203
204 mov w1, #SCBRR_115200BPS_E3_SSCG
205 b 2f
2064:
207 mov w1, #SCBRR_115200BPS
208 b 2f
2093:
210 mov w1, #SCBRR_230400BPS
2112:
212 strb w1, [x0, SCIF_SCBRR]
213#else
214 mov w1, #DL_INIT_DATA
215 strh w1, [x0, #SCIF_DL]
216 mov w1, #CKS_INIT_DATA
217 strh w1, [x0, #SCIF_CKS]
218#endif
219 /* 1-bit interval elapsed */
220 mov w1, #100
2211:
222 subs w1, w1, #1
223 cbnz w1, 1b
224 /*
225 * Set bits RTRG[1:0], TTRG[1:0], and MCE in SCFCR
226 * Clear bits FRST and RFRST to 0
227 */
228 mov w1, #SCFCR_INIT_DATA
229 strh w1, [x0, #SCIF_SCFCR]
230 /* Set bits TE and RE in SCSCR to 1 */
231 ldrh w1, [x0, #SCIF_SCSCR]
232 orr w1, w1, #(SCSCR_TE_EN + SCSCR_RE_EN)
233 strh w1, [x0, #SCIF_SCSCR]
234 mov x0, #1
235
236 ret
237endfunc console_core_init
238
239 /* ---------------------------------------------
240 * int console_putc(int c)
241 * Function to output a character over the
242 * console. It returns the character printed on
243 * success or -1 on error.
244 * In : x0 - character to be printed
245 * Out : return -1 on error else return character.
246 * Clobber list : x1, x2
247 * ---------------------------------------------
248 */
249func console_putc
250 b console_core_putc
251endfunc console_putc
252
253 /* --------------------------------------------------------
254 * int console_core_putc(int c, unsigned int base_addr)
255 * Function to output a character over the console. It
256 * returns the character printed on success or -1 on error.
257 * In : w0 - character to be printed
258 * x1 - console base address
259 * Out : return -1 on error else return character.
260 * Clobber list : x2
261 * --------------------------------------------------------
262 */
263func console_core_putc
264 ldr x1, =SCIF2_BASE
265 cmp w0, #0xA
266 /* Prepend '\r' to '\n' */
267 bne 2f
2681:
269 /* Check if the transmit FIFO is full */
270 ldrh w2, [x1, #SCIF_SCFDR]
271 ubfx w2, w2, #8, #5
272 cmp w2, #16
273 bcs 1b
274 mov w2, #0x0D
275 strb w2, [x1, #SCIF_SCFTDR]
2762:
277 /* Check if the transmit FIFO is full */
278 ldrh w2, [x1, #SCIF_SCFDR]
279 ubfx w2, w2, #8, #5
280 cmp w2, #16
281 bcs 2b
282 strb w0, [x1, #SCIF_SCFTDR]
283
284 ret
285endfunc console_core_putc
286
287 /* ---------------------------------------------
288 * int console_getc(void)
289 * Function to get a character from the console.
290 * It returns the character grabbed on success
291 * or -1 on error.
292 * Clobber list : x0, x1
293 * ---------------------------------------------
294 */
295func console_getc
296 mov w0, #-1
297 ret
298endfunc console_getc
299
300 /* ---------------------------------------------
301 * int console_flush(void)
302 * Function to force a write of all buffered
303 * data that hasn't been output. It returns 0
304 * upon successful completion, otherwise it
305 * returns -1.
306 * Clobber list : x0, x1
307 * ---------------------------------------------
308 */
309func console_flush
310 ldr x0, =SCIF2_BASE
3111:
312 ldrh w1, [x0, #SCIF_SCFDR]
313 ubfx w1, w1, #8, #5
314 cmp w1, #0
315 bne 1b
316
317 mov x0, #100
318 mov x3, x30
319 bl rcar_micro_delay
320 mov x30, x3
321
322 ldr x0, =SCIF2_BASE
323 ldrh w1, [x0, #SCIF_SCSCR]
324 and w1, w1, #~(SCSCR_TE_EN + SCSCR_RE_EN)
325 strh w1, [x0, #SCIF_SCSCR]
326
327 mov w0, #0
328 ret
329endfunc console_flush