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Roberto Vargas52207802017-11-17 13:22:18 +00001/*
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -06002 * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
Roberto Vargas52207802017-11-17 13:22:18 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00006
Daniel Boulby45a2c9e2018-07-06 16:54:44 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <drivers/generic_delay_timer.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000010#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <plat/common/platform.h>
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +000012#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013
Roberto Vargas52207802017-11-17 13:22:18 +000014#pragma weak bl2_el3_early_platform_setup
15#pragma weak bl2_el3_plat_arch_setup
16#pragma weak bl2_el3_plat_prepare_exit
17
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010018#define MAP_BL2_EL3_TOTAL MAP_REGION_FLAT( \
19 bl2_el3_tzram_layout.total_base, \
20 bl2_el3_tzram_layout.total_size, \
21 MT_MEMORY | MT_RW | MT_SECURE)
22
Roberto Vargas52207802017-11-17 13:22:18 +000023static meminfo_t bl2_el3_tzram_layout;
24
25/*
26 * Perform arm specific early platform setup. At this moment we only initialize
27 * the console and the memory layout.
28 */
29void arm_bl2_el3_early_platform_setup(void)
30{
31 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010032 arm_console_boot_init();
Roberto Vargas52207802017-11-17 13:22:18 +000033
34 /*
35 * Allow BL2 to see the whole Trusted RAM. This is determined
36 * statically since we cannot rely on BL1 passing this information
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060037 * in the RESET_TO_BL2 case.
Roberto Vargas52207802017-11-17 13:22:18 +000038 */
39 bl2_el3_tzram_layout.total_base = ARM_BL_RAM_BASE;
40 bl2_el3_tzram_layout.total_size = ARM_BL_RAM_SIZE;
41
42 /* Initialise the IO layer and register platform IO devices */
43 plat_arm_io_setup();
44}
45
46void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
47 u_register_t arg1 __unused,
48 u_register_t arg2 __unused,
49 u_register_t arg3 __unused)
50{
51 arm_bl2_el3_early_platform_setup();
52
53 /*
54 * Initialize Interconnect for this cluster during cold boot.
55 * No need for locks as no other CPU is active.
56 */
57 plat_arm_interconnect_init();
58 /*
59 * Enable Interconnect coherency for the primary CPU's cluster.
60 */
61 plat_arm_interconnect_enter_coherency();
62
63 generic_delay_timer_init();
64}
65
66/*******************************************************************************
67 * Perform the very early platform specific architectural setup here. At the
68 * moment this is only initializes the mmu in a quick and dirty way.
69 ******************************************************************************/
70void arm_bl2_el3_plat_arch_setup(void)
71{
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010072
Roberto Vargas52207802017-11-17 13:22:18 +000073#if USE_COHERENT_MEM
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060074 /* Ensure ARM platforms dont use coherent memory
75 * in RESET_TO_BL2
76 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010077 assert(BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE == 0U);
Roberto Vargas52207802017-11-17 13:22:18 +000078#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010079
80 const mmap_region_t bl_regions[] = {
81 MAP_BL2_EL3_TOTAL,
Daniel Boulby4e97abd2018-07-16 14:09:15 +010082 ARM_MAP_BL_RO,
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010083 {0}
84 };
85
Roberto Vargas344ff022018-10-19 16:44:18 +010086 setup_page_tables(bl_regions, plat_arm_get_mmap());
Roberto Vargas52207802017-11-17 13:22:18 +000087
Julius Werner8e0ef0f2019-07-09 14:02:43 -070088#ifdef __aarch64__
Roberto Vargas52207802017-11-17 13:22:18 +000089 enable_mmu_el3(0);
Julius Werner8e0ef0f2019-07-09 14:02:43 -070090#else
91 enable_mmu_svc_mon(0);
Roberto Vargas52207802017-11-17 13:22:18 +000092#endif
93}
94
95void bl2_el3_plat_arch_setup(void)
96{
97 arm_bl2_el3_plat_arch_setup();
98}
99
100void bl2_el3_plat_prepare_exit(void)
101{
102}