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git01.mediatek.com / filogic / atf / 33c2524569e1418a3aabafb72feeeede491d1ba5 / . / plat / nvidia / tegra / soc / t186 / platform_t186.mk
blob: 5275b8e65434237369c0acbc15a88b8f126c6914 [file] [log] [blame]
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]1#
Varun Wadekarbe57abb2019-01-03 10:44:22 -0800[diff] [blame]2# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekarbf601c22018-06-12 16:55:06 -0700[diff] [blame]3# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]4#
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]5# SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]6#
7
8# platform configs
Varun Wadekara0f26972016-03-11 17:18:51 -0800[diff] [blame]9ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 1
10$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS))
11
Varun Wadekarad2824f2016-03-28 13:44:35 -0700[diff] [blame]12ENABLE_CHIP_VERIFICATION_HARNESS := 0
13$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS))
14
Varun Wadekar94701ff2016-05-23 11:47:34 -0700[diff] [blame]15RESET_TO_BL31 := 1
16
Varun Wadekarf3d9b842018-08-09 15:11:23 -0700[diff] [blame]17PROGRAMMABLE_RESET_ADDRESS := 0
Varun Wadekar94701ff2016-05-23 11:47:34 -0700[diff] [blame]18
19COLD_BOOT_SINGLE_CPU := 1
20
Varun Wadekar0ed62702018-06-20 14:30:59 -0700[diff] [blame]21RELOCATE_BL32_IMAGE := 1
22
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]23# platform settings
Varun Wadekar94d85322015-11-30 12:05:04 -0800[diff] [blame]24TZDRAM_BASE := 0x30000000
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]25$(eval $(call add_define,TZDRAM_BASE))
26
27PLATFORM_CLUSTER_COUNT := 2
28$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
29
30PLATFORM_MAX_CPUS_PER_CLUSTER := 4
31$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
32
Jeetesh Burman29e03be2018-05-31 14:15:30 +0530[diff] [blame]33MAX_XLAT_TABLES := 25
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]34$(eval $(call add_define,MAX_XLAT_TABLES))
35
Varun Wadekar58921252020-03-25 16:19:39 -0700[diff] [blame]36MAX_MMAP_REGIONS := 30
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]37$(eval $(call add_define,MAX_MMAP_REGIONS))
38
39# platform files
Varun Wadekar26dfb512019-01-17 16:36:23 -0800[diff] [blame]40PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t186 \
41 -I${SOC_DIR}/drivers/include
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]42
Varun Wadekar8b1068b2020-02-26 14:52:01 -0800[diff] [blame]43BL31_SOURCES += ${TEGRA_GICv2_SOURCES} \
44 drivers/ti/uart/aarch64/16550_console.S \
Varun Wadekar50a33032017-11-15 15:46:38 -0800[diff] [blame]45 lib/cpus/aarch64/denver.S \
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]46 lib/cpus/aarch64/cortex_a57.S \
Varun Wadekar0c9105e2019-06-13 15:32:11 -0700[diff] [blame]47 ${TEGRA_DRIVERS}/bpmp_ipc/intf.c \
48 ${TEGRA_DRIVERS}/bpmp_ipc/ivc.c \
49 ${TEGRA_DRIVERS}/gpcdma/gpcdma.c \
50 ${TEGRA_DRIVERS}/memctrl/memctrl_v2.c \
51 ${TEGRA_DRIVERS}/smmu/smmu.c \
Varun Wadekara0352ab2017-03-14 14:24:35 -0700[diff] [blame]52 ${SOC_DIR}/drivers/mce/mce.c \
53 ${SOC_DIR}/drivers/mce/ari.c \
54 ${SOC_DIR}/drivers/mce/nvg.c \
55 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
Varun Wadekar0c9105e2019-06-13 15:32:11 -0700[diff] [blame]56 $(SOC_DIR)/drivers/se/se.c \
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530[diff] [blame]57 ${SOC_DIR}/plat_memctrl.c \
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]58 ${SOC_DIR}/plat_psci_handlers.c \
59 ${SOC_DIR}/plat_setup.c \
60 ${SOC_DIR}/plat_secondary.c \
Varun Wadekar93bed2a2016-03-18 13:07:33 -0700[diff] [blame]61 ${SOC_DIR}/plat_sip_calls.c \
Pritesh Raithathac88654f2017-01-02 20:11:32 +0530[diff] [blame]62 ${SOC_DIR}/plat_smmu.c \
Varun Wadekar93bed2a2016-03-18 13:07:33 -0700[diff] [blame]63 ${SOC_DIR}/plat_trampoline.S
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530[diff] [blame]64
Varun Wadekarb01d3bb2017-07-25 13:29:52 -0700[diff] [blame]65# Enable workarounds for selected Cortex-A57 erratas.
66A57_DISABLE_NON_TEMPORAL_HINT := 1
67ERRATA_A57_806969 := 1
68ERRATA_A57_813419 := 1
69ERRATA_A57_813420 := 1
70ERRATA_A57_826974 := 1
71ERRATA_A57_826977 := 1
72ERRATA_A57_828024 := 1
73ERRATA_A57_829520 := 1
74ERRATA_A57_833471 := 1
Varun Wadekarbf601c22018-06-12 16:55:06 -0700[diff] [blame]75
76# Enable higher performance Non-cacheable load forwarding
77A57_ENABLE_NONCACHEABLE_LOAD_FWD := 1