| Haojian Zhuang | 602362d | 2017-06-01 12:15:14 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 6 | #ifndef HI3660_CRG_H |
| 7 | #define HI3660_CRG_H |
| Haojian Zhuang | 602362d | 2017-06-01 12:15:14 +0800 | [diff] [blame] | 8 | |
| 9 | #define CRG_REG_BASE 0xFFF35000 |
| 10 | |
| 11 | #define CRG_PEREN0_REG (CRG_REG_BASE + 0x000) |
| 12 | #define CRG_PERDIS0_REG (CRG_REG_BASE + 0x004) |
| 13 | #define CRG_PERSTAT0_REG (CRG_REG_BASE + 0x008) |
| Justin Chadwell | 01715f9 | 2019-07-11 09:35:01 +0100 | [diff] [blame] | 14 | #define PEREN0_GT_CLK_AOMM (1U << 31) |
| Haojian Zhuang | 602362d | 2017-06-01 12:15:14 +0800 | [diff] [blame] | 15 | |
| 16 | #define CRG_PEREN1_REG (CRG_REG_BASE + 0x010) |
| 17 | #define CRG_PERDIS1_REG (CRG_REG_BASE + 0x014) |
| 18 | #define CRG_PERSTAT1_REG (CRG_REG_BASE + 0x018) |
| 19 | #define CRG_PEREN2_REG (CRG_REG_BASE + 0x020) |
| 20 | #define CRG_PERDIS2_REG (CRG_REG_BASE + 0x024) |
| 21 | #define CRG_PERSTAT2_REG (CRG_REG_BASE + 0x028) |
| 22 | #define PEREN2_HKADCSSI (1 << 24) |
| 23 | |
| 24 | #define CRG_PEREN3_REG (CRG_REG_BASE + 0x030) |
| 25 | #define CRG_PERDIS3_REG (CRG_REG_BASE + 0x034) |
| 26 | |
| 27 | #define CRG_PEREN4_REG (CRG_REG_BASE + 0x040) |
| 28 | #define CRG_PERDIS4_REG (CRG_REG_BASE + 0x044) |
| 29 | #define CRG_PERCLKEN4_REG (CRG_REG_BASE + 0x048) |
| 30 | #define CRG_PERSTAT4_REG (CRG_REG_BASE + 0x04C) |
| 31 | #define GT_ACLK_USB3OTG (1 << 1) |
| 32 | #define GT_CLK_USB3OTG_REF (1 << 0) |
| 33 | |
| 34 | #define CRG_PEREN5_REG (CRG_REG_BASE + 0x050) |
| 35 | #define CRG_PERDIS5_REG (CRG_REG_BASE + 0x054) |
| 36 | #define CRG_PERSTAT5_REG (CRG_REG_BASE + 0x058) |
| 37 | #define CRG_PERRSTEN0_REG (CRG_REG_BASE + 0x060) |
| 38 | #define CRG_PERRSTDIS0_REG (CRG_REG_BASE + 0x064) |
| 39 | #define CRG_PERRSTSTAT0_REG (CRG_REG_BASE + 0x068) |
| 40 | #define CRG_PERRSTEN1_REG (CRG_REG_BASE + 0x06C) |
| 41 | #define CRG_PERRSTDIS1_REG (CRG_REG_BASE + 0x070) |
| 42 | #define CRG_PERRSTSTAT1_REG (CRG_REG_BASE + 0x074) |
| 43 | #define CRG_PERRSTEN2_REG (CRG_REG_BASE + 0x078) |
| 44 | #define CRG_PERRSTDIS2_REG (CRG_REG_BASE + 0x07C) |
| 45 | #define CRG_PERRSTSTAT2_REG (CRG_REG_BASE + 0x080) |
| 46 | #define PERRSTEN2_HKADCSSI (1 << 24) |
| 47 | |
| 48 | #define CRG_PERRSTEN3_REG (CRG_REG_BASE + 0x084) |
| 49 | #define CRG_PERRSTDIS3_REG (CRG_REG_BASE + 0x088) |
| 50 | #define CRG_PERRSTSTAT3_REG (CRG_REG_BASE + 0x08C) |
| 51 | #define CRG_PERRSTEN4_REG (CRG_REG_BASE + 0x090) |
| 52 | #define CRG_PERRSTDIS4_REG (CRG_REG_BASE + 0x094) |
| 53 | #define CRG_PERRSTSTAT4_REG (CRG_REG_BASE + 0x098) |
| 54 | #define IP_RST_USB3OTG_MUX (1 << 8) |
| 55 | #define IP_RST_USB3OTG_AHBIF (1 << 7) |
| 56 | #define IP_RST_USB3OTG_32K (1 << 6) |
| 57 | #define IP_RST_USB3OTG (1 << 5) |
| 58 | #define IP_RST_USB3OTGPHY_POR (1 << 3) |
| 59 | |
| 60 | #define CRG_PERRSTEN5_REG (CRG_REG_BASE + 0x09C) |
| 61 | #define CRG_PERRSTDIS5_REG (CRG_REG_BASE + 0x0A0) |
| 62 | #define CRG_PERRSTSTAT5_REG (CRG_REG_BASE + 0x0A4) |
| 63 | |
| 64 | /* bit fields in CRG_PERI */ |
| Justin Chadwell | 01715f9 | 2019-07-11 09:35:01 +0100 | [diff] [blame] | 65 | #define PERI_PCLK_PCTRL_BIT (1U << 31) |
| Haojian Zhuang | 602362d | 2017-06-01 12:15:14 +0800 | [diff] [blame] | 66 | #define PERI_TIMER12_BIT (1 << 25) |
| 67 | #define PERI_TIMER11_BIT (1 << 24) |
| 68 | #define PERI_TIMER10_BIT (1 << 23) |
| 69 | #define PERI_TIMER9_BIT (1 << 22) |
| 70 | #define PERI_UART5_BIT (1 << 15) |
| 71 | #define PERI_UFS_BIT (1 << 12) |
| 72 | #define PERI_ARST_UFS_BIT (1 << 7) |
| 73 | #define PERI_PPLL2_EN_CPU (1 << 3) |
| 74 | #define PERI_PWM_BIT (1 << 0) |
| 75 | #define PERI_DDRC_BIT (1 << 0) |
| 76 | #define PERI_DDRC_D_BIT (1 << 4) |
| 77 | #define PERI_DDRC_C_BIT (1 << 3) |
| 78 | #define PERI_DDRC_B_BIT (1 << 2) |
| 79 | #define PERI_DDRC_A_BIT (1 << 1) |
| 80 | #define PERI_DDRC_DMUX_BIT (1 << 0) |
| 81 | |
| 82 | #define CRG_CLKDIV0_REG (CRG_REG_BASE + 0x0A0) |
| 83 | #define SC_DIV_LPMCU_MASK ((0x1F << 5) << 16) |
| 84 | #define SC_DIV_LPMCU(x) (((x) & 0x1F) << 5) |
| 85 | |
| 86 | #define CRG_CLKDIV1_REG (CRG_REG_BASE + 0x0B0) |
| 87 | #define SEL_LPMCU_PLL_MASK ((1 << 1) << 16) |
| 88 | #define SEL_SYSBUS_MASK ((1 << 0) << 16) |
| 89 | #define SEL_LPMCU_PLL1 (1 << 1) |
| 90 | #define SEL_LPMCU_PLL0 (0 << 1) |
| 91 | #define SEL_SYSBUS_PLL0 (1 << 0) |
| 92 | #define SEL_SYSBUS_PLL1 (0 << 0) |
| 93 | |
| 94 | #define CRG_CLKDIV3_REG (CRG_REG_BASE + 0x0B4) |
| 95 | #define CRG_CLKDIV5_REG (CRG_REG_BASE + 0x0BC) |
| 96 | #define CRG_CLKDIV8_REG (CRG_REG_BASE + 0x0C8) |
| 97 | |
| 98 | #define CRG_CLKDIV12_REG (CRG_REG_BASE + 0x0D8) |
| 99 | #define SC_DIV_A53HPM_MASK (0x7 << 13) |
| 100 | #define SC_DIV_A53HPM(x) (((x) & 0x7) << 13) |
| 101 | |
| 102 | #define CRG_CLKDIV16_REG (CRG_REG_BASE + 0x0E8) |
| 103 | #define DDRC_CLK_SW_REQ_CFG_MASK (0x3 << 12) |
| 104 | #define DDRC_CLK_SW_REQ_CFG(x) (((x) & 0x3) << 12) |
| 105 | #define SC_DIV_UFSPHY_CFG_MASK (0x3 << 9) |
| 106 | #define SC_DIV_UFSPHY_CFG(x) (((x) & 0x3) << 9) |
| 107 | #define DDRCPLL_SW (1 << 8) |
| 108 | |
| 109 | #define CRG_CLKDIV17_REG (CRG_REG_BASE + 0x0EC) |
| 110 | #define SC_DIV_UFS_PERIBUS (1 << 14) |
| 111 | |
| 112 | #define CRG_CLKDIV18_REG (CRG_REG_BASE + 0x0F0) |
| 113 | #define CRG_CLKDIV19_REG (CRG_REG_BASE + 0x0F4) |
| 114 | #define CRG_CLKDIV20_REG (CRG_REG_BASE + 0x0F8) |
| 115 | #define CLKDIV20_GT_CLK_AOMM (1 << 3) |
| 116 | |
| 117 | #define CRG_CLKDIV22_REG (CRG_REG_BASE + 0x100) |
| 118 | #define SEL_PLL_320M_MASK (1 << 16) |
| 119 | #define SEL_PLL2_320M (1 << 0) |
| 120 | #define SEL_PLL0_320M (0 << 0) |
| 121 | |
| 122 | #define CRG_CLKDIV23_REG (CRG_REG_BASE + 0x104) |
| 123 | #define PERI_DDRC_SW_BIT (1 << 13) |
| 124 | #define DIV_CLK_DDRSYS_MASK (0x3 << 10) |
| 125 | #define DIV_CLK_DDRSYS(x) (((x) & 0x3) << 10) |
| 126 | #define GET_DIV_CLK_DDRSYS(x) (((x) & DIV_CLK_DDRSYS_MASK) >> 10) |
| 127 | #define DIV_CLK_DDRCFG_MASK (0x6 << 5) |
| 128 | #define DIV_CLK_DDRCFG(x) (((x) & 0x6) << 5) |
| 129 | #define GET_DIV_CLK_DDRCFG(x) (((x) & DIV_CLK_DDRCFG_MASK) >> 5) |
| 130 | #define DIV_CLK_DDRC_MASK 0x1F |
| 131 | #define DIV_CLK_DDRC(x) ((x) & DIV_CLK_DDRC_MASK) |
| 132 | #define GET_DIV_CLK_DDRC(x) ((x) & DIV_CLK_DDRC_MASK) |
| 133 | |
| 134 | #define CRG_CLKDIV25_REG (CRG_REG_BASE + 0x10C) |
| 135 | #define DIV_SYSBUS_PLL_MASK (0xF << 16) |
| 136 | #define DIV_SYSBUS_PLL(x) ((x) & 0xF) |
| 137 | |
| 138 | #define CRG_PERI_CTRL2_REG (CRG_REG_BASE + 0x128) |
| 139 | #define PERI_TIME_STAMP_CLK_MASK (0x7 << 28) |
| 140 | #define PERI_TIME_STAMP_CLK_DIV(x) (((x) & 0x7) << 22) |
| 141 | |
| 142 | #define CRG_ISODIS_REG (CRG_REG_BASE + 0x148) |
| 143 | #define CRG_PERPWREN_REG (CRG_REG_BASE + 0x150) |
| 144 | |
| 145 | #define CRG_PEREN7_REG (CRG_REG_BASE + 0x420) |
| 146 | #define CRG_PERDIS7_REG (CRG_REG_BASE + 0x424) |
| 147 | #define CRG_PERSTAT7_REG (CRG_REG_BASE + 0x428) |
| 148 | #define GT_CLK_UFSPHY_CFG (1 << 14) |
| 149 | |
| 150 | #define CRG_PEREN8_REG (CRG_REG_BASE + 0x430) |
| 151 | #define CRG_PERDIS8_REG (CRG_REG_BASE + 0x434) |
| 152 | #define CRG_PERSTAT8_REG (CRG_REG_BASE + 0x438) |
| 153 | #define PERI_DMC_D_BIT (1 << 22) |
| 154 | #define PERI_DMC_C_BIT (1 << 21) |
| 155 | #define PERI_DMC_B_BIT (1 << 20) |
| 156 | #define PERI_DMC_A_BIT (1 << 19) |
| 157 | #define PERI_DMC_BIT (1 << 18) |
| 158 | |
| 159 | #define CRG_PEREN11_REG (CRG_REG_BASE + 0x460) |
| 160 | #define PPLL1_GATE_CPU (1 << 18) |
| 161 | |
| 162 | #define CRG_PERSTAT11_REG (CRG_REG_BASE + 0x46C) |
| 163 | #define PPLL3_EN_STAT (1 << 21) |
| 164 | #define PPLL2_EN_STAT (1 << 20) |
| 165 | #define PPLL1_EN_STAT (1 << 19) |
| 166 | |
| 167 | #define CRG_IVP_SEC_RSTDIS_REG (CRG_REG_BASE + 0xC04) |
| 168 | #define CRG_ISP_SEC_RSTDIS_REG (CRG_REG_BASE + 0xC84) |
| 169 | |
| 170 | #define CRG_RVBAR(c, n) (0xE00 + (0x10 * c) + (0x4 * n)) |
| 171 | #define CRG_GENERAL_SEC_RSTEN_REG (CRG_REG_BASE + 0xE20) |
| 172 | #define CRG_GENERAL_SEC_RSTDIS_REG (CRG_REG_BASE + 0xE24) |
| 173 | #define IP_RST_GPIO0_SEC (1 << 2) |
| 174 | |
| 175 | #define CRG_GENERAL_SEC_CLKDIV0_REG (CRG_REG_BASE + 0xE90) |
| 176 | #define SC_DIV_AO_HISE_MASK 3 |
| 177 | #define SC_DIV_AO_HISE(x) ((x) & 0x3) |
| 178 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 179 | #endif /* HI3660_CRG_H */ |