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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handleyed6ff952014-05-14 17:44:19 +010031#include <platform_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000035ENTRY(bl31_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010036
37
38MEMORY {
Juan Castillo0c70c572014-08-12 13:04:43 +010039 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT
Achin Gupta4f6ad662013-10-25 09:08:21 +010040}
41
42
43SECTIONS
44{
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000045 . = BL31_BASE;
46 ASSERT(. == ALIGN(4096),
47 "BL31_BASE address is not aligned on a page boundary.")
Achin Gupta4f6ad662013-10-25 09:08:21 +010048
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000049 ro . : {
50 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000051 *bl31_entrypoint.o(.text*)
52 *(.text*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000053 *(.rodata*)
Achin Gupta7421b462014-02-01 18:53:26 +000054
Andrew Thoelkee01ea342014-03-18 07:13:52 +000055 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
Achin Gupta7421b462014-02-01 18:53:26 +000056 . = ALIGN(8);
57 __RT_SVC_DESCS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000058 KEEP(*(rt_svc_descs))
Achin Gupta7421b462014-02-01 18:53:26 +000059 __RT_SVC_DESCS_END__ = .;
60
Soby Mathewc704cbc2014-08-14 11:33:56 +010061 /*
62 * Ensure 8-byte alignment for cpu_ops so that its fields are also
63 * aligned. Also ensure cpu_ops inclusion.
64 */
65 . = ALIGN(8);
66 __CPU_OPS_START__ = .;
67 KEEP(*(cpu_ops))
68 __CPU_OPS_END__ = .;
69
Achin Guptab739f222014-01-18 16:50:09 +000070 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000071 __RO_END_UNALIGNED__ = .;
72 /*
73 * Memory page(s) mapped to this section will be marked as read-only,
74 * executable. No RW data from the next section must creep in.
75 * Ensure the rest of the current memory page is unused.
76 */
77 . = NEXT(4096);
78 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010079 } >RAM
80
Soby Mathewc704cbc2014-08-14 11:33:56 +010081 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
82 "cpu_ops not defined for this platform.")
83
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000084 .data . : {
85 __DATA_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000086 *(.data*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000087 __DATA_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010088 } >RAM
89
Sandrine Bailleuxe2e0c652014-06-16 16:12:27 +010090#ifdef BL31_PROGBITS_LIMIT
91 ASSERT(. <= BL31_PROGBITS_LIMIT, "BL3-1 progbits has exceeded its limit.")
92#endif
93
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000094 stacks (NOLOAD) : {
95 __STACKS_START__ = .;
96 *(tzfw_normal_stacks)
97 __STACKS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010098 } >RAM
99
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000100 /*
101 * The .bss section gets initialised to 0 at runtime.
102 * Its base address must be 16-byte aligned.
103 */
104 .bss : ALIGN(16) {
105 __BSS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +0000106 *(.bss*)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100107 *(COMMON)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000108 __BSS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100109 } >RAM
110
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000111 /*
Jeenu Viswambharan97cc9ee2014-02-24 15:20:28 +0000112 * The xlat_table section is for full, aligned page tables (4K).
Achin Guptaa0cd9892014-02-09 13:30:38 +0000113 * Removing them from .bss avoids forcing 4K alignment on
114 * the .bss section and eliminates the unecessary zero init
115 */
116 xlat_table (NOLOAD) : {
117 *(xlat_table)
118 } >RAM
119
120 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000121 * The base address of the coherent memory section must be page-aligned (4K)
122 * to guarantee that the coherent data are stored on their own pages and
123 * are not mixed with normal data. This is required to set up the correct
124 * memory attributes for the coherent data page tables.
125 */
126 coherent_ram (NOLOAD) : ALIGN(4096) {
127 __COHERENT_RAM_START__ = .;
128 *(tzfw_coherent_mem)
129 __COHERENT_RAM_END_UNALIGNED__ = .;
130 /*
131 * Memory page(s) mapped to this section will be marked
132 * as device memory. No other unexpected data must creep in.
133 * Ensure the rest of the current memory page is unused.
134 */
135 . = NEXT(4096);
136 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100137 } >RAM
Achin Gupta4f6ad662013-10-25 09:08:21 +0100138
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000139 __BL31_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100140
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000141 __BSS_SIZE__ = SIZEOF(.bss);
142 __COHERENT_RAM_UNALIGNED_SIZE__ =
143 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100145 ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100146}