Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 1 | /* |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __PLATFORM_DEF_H__ |
| 32 | #define __PLATFORM_DEF_H__ |
| 33 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 34 | #include <arm_def.h> |
| 35 | #include <board_arm_def.h> |
| 36 | #include <common_def.h> |
| 37 | #include <tzc400.h> |
| 38 | #include <v2m_def.h> |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 39 | #include "../fvp_def.h" |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 40 | |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 41 | /* Required platform porting definitions */ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 42 | #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 43 | PLATFORM_CORE_COUNT) |
| 44 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 45 | #define PLATFORM_CORE_COUNT (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 46 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 47 | /* |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 48 | * Other platform porting definitions are provided by included headers |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 49 | */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 50 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 51 | /* |
| 52 | * Required ARM standard platform porting definitions |
| 53 | */ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 54 | #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 55 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 56 | #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 |
| 57 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 58 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 59 | #define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000 |
| 60 | #define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 61 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 62 | /* No SCP in FVP */ |
| 63 | #define PLAT_ARM_SCP_TZC_DRAM1_SIZE MAKE_ULL(0x0) |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 64 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 65 | #define PLAT_ARM_DRAM2_SIZE MAKE_ULL(0x780000000) |
Juan Castillo | d227d8b | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 66 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 67 | /* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 68 | * Load address of BL33 for this platform port |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 69 | */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 70 | #define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + 0x8000000) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 71 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 72 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 73 | /* |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 74 | * PL011 related constants |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 75 | */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 76 | #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE |
| 77 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 78 | |
Soby Mathew | 2fd66be | 2015-12-09 11:38:43 +0000 | [diff] [blame] | 79 | #define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE |
| 80 | #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ |
| 81 | |
| 82 | #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE |
| 83 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 84 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 85 | #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE |
| 86 | #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 87 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 88 | /* CCI related constants */ |
| 89 | #define PLAT_ARM_CCI_BASE 0x2c090000 |
| 90 | #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 |
| 91 | #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 |
Juan Castillo | e33ee5f | 2014-12-19 09:51:00 +0000 | [diff] [blame] | 92 | |
Soby Mathew | 7356b1e | 2016-03-24 10:12:42 +0000 | [diff] [blame] | 93 | /* CCN related constants. Only CCN 502 is currently supported */ |
| 94 | #define PLAT_ARM_CCN_BASE 0x2e000000 |
| 95 | #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 |
| 96 | |
Vikram Kanigiri | a2cee03 | 2015-07-31 16:35:05 +0100 | [diff] [blame] | 97 | /* System timer related constants */ |
| 98 | #define PLAT_ARM_NSTIMER_FRAME_ID 1 |
| 99 | |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 100 | /* Mailbox base address */ |
| 101 | #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE |
| 102 | |
| 103 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 104 | /* TrustZone controller related constants |
| 105 | * |
| 106 | * Currently only filters 0 and 2 are connected on Base FVP. |
| 107 | * Filter 0 : CPU clusters (no access to DRAM by default) |
| 108 | * Filter 1 : not connected |
| 109 | * Filter 2 : LCDs (access to VRAM allowed by default) |
| 110 | * Filter 3 : not connected |
| 111 | * Programming unconnected filters will have no effect at the |
| 112 | * moment. These filter could, however, be connected in future. |
| 113 | * So care should be taken not to configure the unused filters. |
| 114 | * |
| 115 | * Allow only non-secure access to all DRAM to supported devices. |
| 116 | * Give access to the CPUs and Virtio. Some devices |
| 117 | * would normally use the default ID so allow that too. |
| 118 | */ |
Vikram Kanigiri | cab2f5e | 2015-07-31 14:50:36 +0100 | [diff] [blame] | 119 | #define PLAT_ARM_TZC_BASE 0x2a4a0000 |
Soby Mathew | 9c708b5 | 2016-02-26 14:23:19 +0000 | [diff] [blame] | 120 | #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 121 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 122 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 123 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ |
| 124 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ |
| 125 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ |
| 126 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ |
| 127 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 128 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 129 | /* |
| 130 | * GIC related constants to cater for both GICv2 and GICv3 instances of an |
| 131 | * FVP. They could be overriden at runtime in case the FVP implements the legacy |
| 132 | * VE memory map. |
| 133 | */ |
| 134 | #define PLAT_ARM_GICD_BASE BASE_GICD_BASE |
| 135 | #define PLAT_ARM_GICR_BASE BASE_GICR_BASE |
| 136 | #define PLAT_ARM_GICC_BASE BASE_GICC_BASE |
| 137 | |
| 138 | /* |
| 139 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 140 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 141 | * as Group 0 interrupts. |
| 142 | */ |
| 143 | #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ |
| 144 | FVP_IRQ_TZ_WDOG, \ |
| 145 | FVP_IRQ_SEC_SYS_TIMER |
| 146 | |
| 147 | #define PLAT_ARM_G0_IRQS ARM_G0_IRQS |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 148 | |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 149 | /* |
| 150 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 151 | * plus a little space for growth. |
| 152 | */ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 153 | #define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000 |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 154 | |
| 155 | /* |
| 156 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 157 | * little space for growth. |
| 158 | */ |
| 159 | #if TRUSTED_BOARD_BOOT |
| 160 | # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 |
| 161 | #else |
| 162 | # define PLAT_ARM_MAX_BL2_SIZE 0xC000 |
| 163 | #endif |
| 164 | |
| 165 | /* |
| 166 | * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a |
| 167 | * little space for growth. |
| 168 | */ |
| 169 | #define PLAT_ARM_MAX_BL31_SIZE 0x1D000 |
| 170 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 171 | #endif /* __PLATFORM_DEF_H__ */ |