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Douglas Raillardd7c21b72017-06-28 15:23:03 +01001ARM Trusted Firmware User Guide
2===============================
3
4
5.. section-numbering::
6 :suffix: .
7
8.. contents::
9
10This document describes how to build ARM Trusted Firmware (TF) and run it with a
11tested set of other software components using defined configurations on the Juno
12ARM development platform and ARM Fixed Virtual Platform (FVP) models. It is
13possible to use other software components, configurations and platforms but that
14is outside the scope of this document.
15
16This document assumes that the reader has previous experience running a fully
17bootable Linux software stack on Juno or FVP using the prebuilt binaries and
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010018filesystems provided by `Linaro`_. Further information may be found in the
19`Linaro instructions`_. It also assumes that the user understands the role of
20the different software components required to boot a Linux system:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
22- Specific firmware images required by the platform (e.g. SCP firmware on Juno)
23- Normal world bootloader (e.g. UEFI or U-Boot)
24- Device tree
25- Linux kernel image
26- Root filesystem
27
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010028This document also assumes that the user is familiar with the `FVP models`_ and
Douglas Raillardd7c21b72017-06-28 15:23:03 +010029the different command line options available to launch the model.
30
31This document should be used in conjunction with the `Firmware Design`_.
32
33Host machine requirements
34-------------------------
35
36The minimum recommended machine specification for building the software and
37running the FVP models is a dual-core processor running at 2GHz with 12GB of
38RAM. For best performance, use a machine with a quad-core processor running at
392.6GHz with 16GB of RAM.
40
41The software has been tested on Ubuntu 14.04 LTS (64-bit). Packages used for
42building the software were installed from that distribution unless otherwise
43specified.
44
45The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
David Cunadob2de0992017-06-29 12:01:33 +010046Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010047
48Tools
49-----
50
51Install the required packages to build Trusted Firmware with the following
52command:
53
54::
55
56 sudo apt-get install build-essential gcc make git libssl-dev
57
David Cunadob2de0992017-06-29 12:01:33 +010058ARM TF has been tested with `Linaro Release 17.04`_.
59
Douglas Raillardd7c21b72017-06-28 15:23:03 +010060Download and install the AArch32 or AArch64 little-endian GCC cross compiler.
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010061The `Linaro Release Notes`_ documents which version of the compiler to use for a
62given Linaro Release. Also, these `Linaro instructions`_ provide further
63guidance and a script, which can be used to download Linaro deliverables
64automatically.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010065
66Optionally, Trusted Firmware can be built using clang or ARM Compiler 6.
67See instructions below on how to switch the default compiler.
68
69In addition, the following optional packages and tools may be needed:
70
71- ``device-tree-compiler`` package if you need to rebuild the Flattened Device
72 Tree (FDT) source files (``.dts`` files) provided with this software.
73
74- For debugging, ARM `Development Studio 5 (DS-5)`_.
75
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010076- To create and modify the diagram files included in the documentation, `Dia`_.
77 This tool can be found in most Linux distributions. Inkscape is needed to
78 generate the actual *.png files.
79
Douglas Raillardd7c21b72017-06-28 15:23:03 +010080Getting the Trusted Firmware source code
81----------------------------------------
82
83Download the Trusted Firmware source code from Github:
84
85::
86
87 git clone https://github.com/ARM-software/arm-trusted-firmware.git
88
89Building the Trusted Firmware
90-----------------------------
91
92- Before building Trusted Firmware, the environment variable ``CROSS_COMPILE``
93 must point to the Linaro cross compiler.
94
95 For AArch64:
96
97 ::
98
99 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
100
101 For AArch32:
102
103 ::
104
105 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
106
107 It is possible to build Trusted Firmware using clang or ARM Compiler 6.
108 To do so ``CC`` needs to point to the clang or armclang binary. Only the
109 compiler is switched; the assembler and linker need to be provided by
110 the GNU toolchain, thus ``CROSS_COMPILE`` should be set as described above.
111
112 ARM Compiler 6 will be selected when the base name of the path assigned
113 to ``CC`` matches the string 'armclang'.
114
115 For AArch64 using ARM Compiler 6:
116
117 ::
118
119 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
120 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
121
122 Clang will be selected when the base name of the path assigned to ``CC``
123 contains the string 'clang'. This is to allow both clang and clang-X.Y
124 to work.
125
126 For AArch64 using clang:
127
128 ::
129
130 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
131 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
132
133- Change to the root directory of the Trusted Firmware source tree and build.
134
135 For AArch64:
136
137 ::
138
139 make PLAT=<platform> all
140
141 For AArch32:
142
143 ::
144
145 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
146
147 Notes:
148
149 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
150 `Summary of build options`_ for more information on available build
151 options.
152
153 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
154
155 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
156 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp\_min, is
157 provided by ARM Trusted Firmware to demonstrate how PSCI Library can
158 be integrated with an AArch32 EL3 Runtime Software. Some AArch32 EL3
159 Runtime Software may include other runtime services, for example
160 Trusted OS services. A guide to integrate PSCI library with AArch32
161 EL3 Runtime Software can be found `here`_.
162
163 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
164 image, is not compiled in by default. Refer to the
165 `Building the Test Secure Payload`_ section below.
166
167 - By default this produces a release version of the build. To produce a
168 debug version instead, refer to the "Debugging options" section below.
169
170 - The build process creates products in a ``build`` directory tree, building
171 the objects and binaries for each boot loader stage in separate
172 sub-directories. The following boot loader binary files are created
173 from the corresponding ELF files:
174
175 - ``build/<platform>/<build-type>/bl1.bin``
176 - ``build/<platform>/<build-type>/bl2.bin``
177 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
178 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
179
180 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
181 is either ``debug`` or ``release``. The actual number of images might differ
182 depending on the platform.
183
184- Build products for a specific build variant can be removed using:
185
186 ::
187
188 make DEBUG=<D> PLAT=<platform> clean
189
190 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
191
192 The build tree can be removed completely using:
193
194 ::
195
196 make realclean
197
198Summary of build options
199~~~~~~~~~~~~~~~~~~~~~~~~
200
201ARM Trusted Firmware build system supports the following build options. Unless
202mentioned otherwise, these options are expected to be specified at the build
203command line and are not to be modified in any component makefiles. Note that
204the build system doesn't track dependency for build options. Therefore, if any
205of the build options are changed from a previous build, a clean build must be
206performed.
207
208Common build options
209^^^^^^^^^^^^^^^^^^^^
210
211- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
212 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
213 directory containing the SP source, relative to the ``bl32/``; the directory
214 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
215
216- ``ARCH`` : Choose the target build architecture for ARM Trusted Firmware.
217 It can take either ``aarch64`` or ``aarch32`` as values. By default, it is
218 defined to ``aarch64``.
219
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100220- ``ARM_ARCH_MAJOR``: The major version of ARM Architecture to target when
221 compiling ARM Trusted Firmware. Its value must be numeric, and defaults to
Etienne Carriere1374fcb2017-11-08 13:48:40 +0100222 8 . See also, *ARMv8 Architecture Extensions* and
223 *ARMv7 Architecture Extensions* in `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100224
225- ``ARM_ARCH_MINOR``: The minor version of ARM Architecture to target when
226 compiling ARM Trusted Firmware. Its value must be a numeric, and defaults
227 to 0. See also, *ARMv8 Architecture Extensions* in `Firmware Design`_.
228
229- ``ARM_GIC_ARCH``: Choice of ARM GIC architecture version used by the ARM
230 Legacy GIC driver for implementing the platform GIC API. This API is used
231 by the interrupt management framework. Default is 2 (that is, version 2.0).
232 This build option is deprecated.
233
234- ``ARM_PLAT_MT``: This flag determines whether the ARM platform layer has to
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000235 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
236 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
237 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
238 this flag is 0. Note that this option is not used on FVP platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100239
240- ``BL2``: This is an optional build option which specifies the path to BL2
241 image for the ``fip`` target. In this case, the BL2 in the ARM Trusted
242 Firmware will not be built.
243
244- ``BL2U``: This is an optional build option which specifies the path to
245 BL2U image. In this case, the BL2U in the ARM Trusted Firmware will not
246 be built.
247
248- ``BL31``: This is an optional build option which specifies the path to
249 BL31 image for the ``fip`` target. In this case, the BL31 in the ARM
250 Trusted Firmware will not be built.
251
252- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
253 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
254 this file name will be used to save the key.
255
256- ``BL32``: This is an optional build option which specifies the path to
257 BL32 image for the ``fip`` target. In this case, the BL32 in the ARM
258 Trusted Firmware will not be built.
259
Summer Qin80726782017-04-20 16:28:39 +0100260- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
261 Trusted OS Extra1 image for the ``fip`` target.
262
263- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
264 Trusted OS Extra2 image for the ``fip`` target.
265
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100266- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
267 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
268 this file name will be used to save the key.
269
270- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
271 ``fip`` target in case the BL2 from ARM Trusted Firmware is used.
272
273- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
274 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
275 this file name will be used to save the key.
276
277- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
278 compilation of each build. It must be set to a C string (including quotes
279 where applicable). Defaults to a string that contains the time and date of
280 the compilation.
281
282- ``BUILD_STRING``: Input string for VERSION\_STRING, which allows the TF build
283 to be uniquely identified. Defaults to the current git commit id.
284
285- ``CFLAGS``: Extra user options appended on the compiler's command line in
286 addition to the options set by the build system.
287
288- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
289 release several CPUs out of reset. It can take either 0 (several CPUs may be
290 brought up) or 1 (only one CPU will ever be brought up during cold reset).
291 Default is 0. If the platform always brings up a single CPU, there is no
292 need to distinguish between primary and secondary CPUs and the boot path can
293 be optimised. The ``plat_is_my_cpu_primary()`` and
294 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
295 to be implemented in this case.
296
297- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
298 register state when an unexpected exception occurs during execution of
299 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
300 this is only enabled for a debug build of the firmware.
301
302- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
303 certificate generation tool to create new keys in case no valid keys are
304 present or specified. Allowed options are '0' or '1'. Default is '1'.
305
306- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
307 the AArch32 system registers to be included when saving and restoring the
308 CPU context. The option must be set to 0 for AArch64-only platforms (that
309 is on hardware that does not implement AArch32, or at least not at EL1 and
310 higher ELs). Default value is 1.
311
312- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
313 registers to be included when saving and restoring the CPU context. Default
314 is 0.
315
316- ``DEBUG``: Chooses between a debug and release build. It can take either 0
317 (release) or 1 (debug) as values. 0 is the default.
318
319- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
320 the normal boot flow. It must specify the entry point address of the EL3
321 payload. Please refer to the "Booting an EL3 payload" section for more
322 details.
323
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100324- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100325 This is an optional architectural feature available on v8.4 onwards. Some
326 v8.2 implementations also implement an AMU and this option can be used to
327 enable this feature on those systems as well. Default is 0.
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100328
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100329- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
330 are compiled out. For debug builds, this option defaults to 1, and calls to
331 ``assert()`` are left in place. For release builds, this option defaults to 0
332 and calls to ``assert()`` function are compiled out. This option can be set
333 independently of ``DEBUG``. It can also be used to hide any auxiliary code
334 that is only required for the assertion and does not fit in the assertion
335 itself.
336
337- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
338 Measurement Framework(PMF). Default is 0.
339
340- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
341 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
342 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
343 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
344 software.
345
346- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
347 instrumentation which injects timestamp collection points into
348 Trusted Firmware to allow runtime performance to be measured.
349 Currently, only PSCI is instrumented. Enabling this option enables
350 the ``ENABLE_PMF`` build option as well. Default is 0.
351
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100352- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100353 extensions. This is an optional architectural feature for AArch64.
354 The default is 1 but is automatically disabled when the target architecture
355 is AArch32.
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100356
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100357- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
358 checks in GCC. Allowed values are "all", "strong" and "0" (default).
359 "strong" is the recommended stack protection level if this feature is
360 desired. 0 disables the stack protection. For all values other than 0, the
361 ``plat_get_stack_protector_canary()`` platform hook needs to be implemented.
362 The value is passed as the last component of the option
363 ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
364
365- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
366 deprecated platform APIs, helper functions or drivers within Trusted
367 Firmware as error. It can take the value 1 (flag the use of deprecated
368 APIs as error) or 0. The default is 0.
369
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100370- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
371 targeted at EL3. When set ``0`` (default), no exceptions are expected or
372 handled at EL3, and a panic will result. This is supported only for AArch64
373 builds.
374
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100375- ``FIP_NAME``: This is an optional build option which specifies the FIP
376 filename for the ``fip`` target. Default is ``fip.bin``.
377
378- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
379 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
380
381- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
382 tool to create certificates as per the Chain of Trust described in
383 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
384 include the certificates in the FIP and FWU\_FIP. Default value is '0'.
385
386 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
387 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
388 the corresponding certificates, and to include those certificates in the
389 FIP and FWU\_FIP.
390
391 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
392 images will not include support for Trusted Board Boot. The FIP will still
393 include the corresponding certificates. This FIP can be used to verify the
394 Chain of Trust on the host machine through other mechanisms.
395
396 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
397 images will include support for Trusted Board Boot, but the FIP and FWU\_FIP
398 will not include the corresponding certificates, causing a boot failure.
399
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100400- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
401 inherent support for specific EL3 type interrupts. Setting this build option
402 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
403 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
404 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
405 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
406 the Secure Payload interrupts needs to be synchronously handed over to Secure
407 EL1 for handling. The default value of this option is ``0``, which means the
408 Group 0 interrupts are assumed to be handled by Secure EL1.
409
410 .. __: `platform-interrupt-controller-API.rst`
411 .. __: `interrupt-framework-design.rst`
412
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100413- ``HANDLE_EA_EL3_FIRST``: When defined External Aborts and SError Interrupts
414 will be always trapped in EL3 i.e. in BL31 at runtime.
415
416- ``HW_ASSISTED_COHERENCY``: On most ARM systems to-date, platform-specific
417 software operations are required for CPUs to enter and exit coherency.
418 However, there exists newer systems where CPUs' entry to and exit from
419 coherency is managed in hardware. Such systems require software to only
420 initiate the operations, and the rest is managed in hardware, minimizing
421 active software management. In such systems, this boolean option enables ARM
422 Trusted Firmware to carry out build and run-time optimizations during boot
423 and power management operations. This option defaults to 0 and if it is
424 enabled, then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
425
426- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
427 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
428 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
429 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
430 images.
431
Soby Mathew13b16052017-08-31 11:49:32 +0100432- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
433 used for generating the PKCS keys and subsequent signing of the certificate.
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800434 It accepts 3 values viz. ``rsa``, ``rsa_1_5``, ``ecdsa``. The ``rsa_1_5`` is
Soby Mathew2fd70f62017-08-31 11:50:29 +0100435 the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is
436 retained only for compatibility. The default value of this flag is ``rsa``
437 which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
Soby Mathew13b16052017-08-31 11:49:32 +0100438
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800439- ``HASH_ALG``: This build flag enables the user to select the secure hash
440 algorithm. It accepts 3 values viz. ``sha256``, ``sha384``, ``sha512``.
441 The default value of this flag is ``sha256``.
442
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100443- ``LDFLAGS``: Extra user options appended to the linkers' command line in
444 addition to the one set by the build system.
445
446- ``LOAD_IMAGE_V2``: Boolean option to enable support for new version (v2) of
447 image loading, which provides more flexibility and scalability around what
448 images are loaded and executed during boot. Default is 0.
449 Note: ``TRUSTED_BOARD_BOOT`` is currently only supported for AArch64 when
450 ``LOAD_IMAGE_V2`` is enabled.
451
452- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
453 output compiled into the build. This should be one of the following:
454
455 ::
456
457 0 (LOG_LEVEL_NONE)
458 10 (LOG_LEVEL_NOTICE)
459 20 (LOG_LEVEL_ERROR)
460 30 (LOG_LEVEL_WARNING)
461 40 (LOG_LEVEL_INFO)
462 50 (LOG_LEVEL_VERBOSE)
463
464 All log output up to and including the log level is compiled into the build.
465 The default value is 40 in debug builds and 20 in release builds.
466
467- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
468 specifies the file that contains the Non-Trusted World private key in PEM
469 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
470
471- ``NS_BL2U``: Path to NS\_BL2U image in the host file system. This image is
472 optional. It is only needed if the platform makefile specifies that it
473 is required in order to build the ``fwu_fip`` target.
474
475- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
476 contents upon world switch. It can take either 0 (don't save and restore) or
477 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
478 wants the timer registers to be saved and restored.
479
480- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
481 the underlying hardware is not a full PL011 UART but a minimally compliant
482 generic UART, which is a subset of the PL011. The driver will not access
483 any register that is not part of the SBSA generic UART specification.
484 Default value is 0 (a full PL011 compliant UART is present).
485
486- ``PLAT``: Choose a platform to build ARM Trusted Firmware for. The chosen
487 platform name must be subdirectory of any depth under ``plat/``, and must
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +0100488 contain a platform makefile named ``platform.mk``. For example to build ARM
489 Trusted Firmware for ARM Juno board select PLAT=juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100490
491- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
492 instead of the normal boot flow. When defined, it must specify the entry
493 point address for the preloaded BL33 image. This option is incompatible with
494 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
495 over ``PRELOADED_BL33_BASE``.
496
497- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
498 vector address can be programmed or is fixed on the platform. It can take
499 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
500 programmable reset address, it is expected that a CPU will start executing
501 code directly at the right address, both on a cold and warm reset. In this
502 case, there is no need to identify the entrypoint on boot and the boot path
503 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
504 does not need to be implemented in this case.
505
506- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
507 possible for the PSCI power-state parameter viz original and extended
508 State-ID formats. This flag if set to 1, configures the generic PSCI layer
509 to use the extended format. The default value of this flag is 0, which
510 means by default the original power-state format is used by the PSCI
511 implementation. This flag should be specified by the platform makefile
512 and it governs the return value of PSCI\_FEATURES API for CPU\_SUSPEND
513 smc function id. When this option is enabled on ARM platforms, the
514 option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well.
515
516- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
517 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
518 entrypoint) or 1 (CPU reset to BL31 entrypoint).
519 The default value is 0.
520
521- ``RESET_TO_SP_MIN``: SP\_MIN is the minimal AArch32 Secure Payload provided in
522 ARM Trusted Firmware. This flag configures SP\_MIN entrypoint as the CPU
523 reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU
524 reset to BL1 entrypoint) or 1 (CPU reset to SP\_MIN entrypoint). The default
525 value is 0.
526
527- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
528 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
529 file name will be used to save the key.
530
531- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
532 certificate generation tool to save the keys used to establish the Chain of
533 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
534
535- ``SCP_BL2``: Path to SCP\_BL2 image in the host file system. This image is optional.
536 If a SCP\_BL2 image is present then this option must be passed for the ``fip``
537 target.
538
539- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
540 file that contains the SCP\_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
541 this file name will be used to save the key.
542
543- ``SCP_BL2U``: Path to SCP\_BL2U image in the host file system. This image is
544 optional. It is only needed if the platform makefile specifies that it
545 is required in order to build the ``fwu_fip`` target.
546
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100547- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
548 Delegated Exception Interface to BL31 image. This defaults to ``0``.
549
550 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
551 set to ``1``.
552
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100553- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
554 isolated on separate memory pages. This is a trade-off between security and
555 memory usage. See "Isolating code and read-only data on separate memory
556 pages" section in `Firmware Design`_. This flag is disabled by default and
557 affects all BL images.
558
559- ``SPD``: Choose a Secure Payload Dispatcher component to be built into the
560 Trusted Firmware. This build option is only valid if ``ARCH=aarch64``. The
561 value should be the path to the directory containing the SPD source,
562 relative to ``services/spd/``; the directory is expected to
563 contain a makefile called ``<spd-value>.mk``.
564
565- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
566 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
567 execution in BL1 just before handing over to BL31. At this point, all
568 firmware images have been loaded in memory, and the MMU and caches are
569 turned off. Refer to the "Debugging options" section for more details.
570
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200571- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
572 secure interrupts (caught through the FIQ line). Platforms can enable
573 this directive if they need to handle such interruption. When enabled,
574 the FIQ are handled in monitor mode and non secure world is not allowed
575 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
576 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
577
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100578- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
579 Boot feature. When set to '1', BL1 and BL2 images include support to load
580 and verify the certificates and images in a FIP, and BL1 includes support
581 for the Firmware Update. The default value is '0'. Generation and inclusion
582 of certificates in the FIP and FWU\_FIP depends upon the value of the
583 ``GENERATE_COT`` option.
584
585 Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys
586 already exist in disk, they will be overwritten without further notice.
587
588- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
589 specifies the file that contains the Trusted World private key in PEM
590 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
591
592- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
593 synchronous, (see "Initializing a BL32 Image" section in
594 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
595 synchronous method) or 1 (BL32 is initialized using asynchronous method).
596 Default is 0.
597
598- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
599 routing model which routes non-secure interrupts asynchronously from TSP
600 to EL3 causing immediate preemption of TSP. The EL3 is responsible
601 for saving and restoring the TSP context in this routing model. The
602 default routing model (when the value is 0) is to route non-secure
603 interrupts to TSP allowing it to save its context and hand over
604 synchronously to EL3 via an SMC.
605
606- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
607 memory region in the BL memory map or not (see "Use of Coherent memory in
608 Trusted Firmware" section in `Firmware Design`_). It can take the value 1
609 (Coherent memory region is included) or 0 (Coherent memory region is
610 excluded). Default is 1.
611
612- ``V``: Verbose build. If assigned anything other than 0, the build commands
613 are printed. Default is 0.
614
615- ``VERSION_STRING``: String used in the log output for each TF image. Defaults
616 to a string formed by concatenating the version number, build type and build
617 string.
618
619- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
620 the CPU after warm boot. This is applicable for platforms which do not
621 require interconnect programming to enable cache coherency (eg: single
622 cluster platforms). If this option is enabled, then warm boot path
623 enables D-caches immediately after enabling MMU. This option defaults to 0.
624
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100625ARM development platform specific build options
626^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
627
628- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
629 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
630 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
631 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
632 flag.
633
634- ``ARM_BOARD_OPTIMISE_MEM``: Boolean option to enable or disable optimisation
635 of the memory reserved for each image. This affects the maximum size of each
636 BL image as well as the number of allocated memory regions and translation
637 tables. By default this flag is 0, which means it uses the default
638 unoptimised values for these macros. ARM development platforms that wish to
639 optimise memory usage need to set this flag to 1 and must override the
640 related macros.
641
642- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
643 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
644 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
645 match the frame used by the Non-Secure image (normally the Linux kernel).
646 Default is true (access to the frame is allowed).
647
648- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
649 By default, ARM platforms use a watchdog to trigger a system reset in case
650 an error is encountered during the boot process (for example, when an image
651 could not be loaded or authenticated). The watchdog is enabled in the early
652 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
653 Trusted Watchdog may be disabled at build time for testing or development
654 purposes.
655
656- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
657 for the construction of composite state-ID in the power-state parameter.
658 The existing PSCI clients currently do not support this encoding of
659 State-ID yet. Hence this flag is used to configure whether to use the
660 recommended State-ID encoding or not. The default value of this flag is 0,
661 in which case the platform is configured to expect NULL in the State-ID
662 field of power-state parameter.
663
664- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
665 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
666 for ARM platforms. Depending on the selected option, the proper private key
667 must be specified using the ``ROT_KEY`` option when building the Trusted
668 Firmware. This private key will be used by the certificate generation tool
669 to sign the BL2 and Trusted Key certificates. Available options for
670 ``ARM_ROTPK_LOCATION`` are:
671
672 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
673 registers. The private key corresponding to this ROTPK hash is not
674 currently available.
675 - ``devel_rsa`` : return a development public key hash embedded in the BL1
676 and BL2 binaries. This hash has been obtained from the RSA public key
677 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
678 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
679 creating the certificates.
Qixiang Xu1c2aef12017-08-24 15:12:20 +0800680 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
681 and BL2 binaries. This hash has been obtained from the ECDSA public key
682 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
683 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
684 when creating the certificates.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100685
686- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
687
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800688 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100689 - ``tdram`` : Trusted DRAM (if available)
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800690 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
691 configured by the TrustZone controller)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100692
693- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile the Trusted Firmware
694 with version 1 of the translation tables library instead of version 2. It is
695 set to 0 by default, which selects version 2.
696
697- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable Trusted Firmware to invoke
698 ARM® TrustZone® CryptoCell functionality for Trusted Board Boot on capable
699 ARM platforms. If this option is specified, then the path to the CryptoCell
700 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
701
702For a better understanding of these options, the ARM development platform memory
703map is explained in the `Firmware Design`_.
704
705ARM CSS platform specific build options
706^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
707
708- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
709 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
710 compatible change to the MTL protocol, used for AP/SCP communication.
711 Trusted Firmware no longer supports earlier SCP versions. If this option is
712 set to 1 then Trusted Firmware will detect if an earlier version is in use.
713 Default is 1.
714
715- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP\_BL2 and
716 SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded
717 during boot. Default is 1.
718
Soby Mathew1ced6b82017-06-12 12:37:10 +0100719- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
720 instead of SCPI/BOM driver for communicating with the SCP during power
721 management operations and for SCP RAM Firmware transfer. If this option
722 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100723
724ARM FVP platform specific build options
725^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
726
727- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
728 build the topology tree within Trusted Firmware. By default the
729 Trusted Firmware is configured for dual cluster topology and this option
730 can be used to override the default value.
731
732- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
733 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
734 explained in the options below:
735
736 - ``FVP_CCI`` : The CCI driver is selected. This is the default
737 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
738 - ``FVP_CCN`` : The CCN driver is selected. This is the default
739 if ``FVP_CLUSTER_COUNT`` > 2.
740
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000741- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
742 in the system. This option defaults to 1. Note that the build option
743 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
744
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100745- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
746
747 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
748 - ``FVP_GICV2`` : The GICv2 only driver is selected
749 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
750 - ``FVP_GICV3_LEGACY``: The Legacy GICv3 driver is selected (deprecated)
751 Note: If Trusted Firmware is compiled with this option on FVPs with
752 GICv3 hardware, then it configures the hardware to run in GICv2
753 emulation mode
754
755- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
756 for functions that wait for an arbitrary time length (udelay and mdelay).
757 The default value is 0.
758
759Debugging options
760~~~~~~~~~~~~~~~~~
761
762To compile a debug version and make the build more verbose use
763
764::
765
766 make PLAT=<platform> DEBUG=1 V=1 all
767
768AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
769example DS-5) might not support this and may need an older version of DWARF
770symbols to be emitted by GCC. This can be achieved by using the
771``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
772version to 2 is recommended for DS-5 versions older than 5.16.
773
774When debugging logic problems it might also be useful to disable all compiler
775optimizations by using ``-O0``.
776
777NOTE: Using ``-O0`` could cause output images to be larger and base addresses
778might need to be recalculated (see the **Memory layout on ARM development
779platforms** section in the `Firmware Design`_).
780
781Extra debug options can be passed to the build system by setting ``CFLAGS`` or
782``LDFLAGS``:
783
784.. code:: makefile
785
786 CFLAGS='-O0 -gdwarf-2' \
787 make PLAT=<platform> DEBUG=1 V=1 all
788
789Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
790ignored as the linker is called directly.
791
792It is also possible to introduce an infinite loop to help in debugging the
793post-BL2 phase of the Trusted Firmware. This can be done by rebuilding BL1 with
Douglas Raillard30d7b362017-06-28 16:14:55 +0100794the ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100795section. In this case, the developer may take control of the target using a
796debugger when indicated by the console output. When using DS-5, the following
797commands can be used:
798
799::
800
801 # Stop target execution
802 interrupt
803
804 #
805 # Prepare your debugging environment, e.g. set breakpoints
806 #
807
808 # Jump over the debug loop
809 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
810
811 # Resume execution
812 continue
813
814Building the Test Secure Payload
815~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
816
817The TSP is coupled with a companion runtime service in the BL31 firmware,
818called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
819must be recompiled as well. For more information on SPs and SPDs, see the
820`Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
821
822First clean the Trusted Firmware build directory to get rid of any previous
823BL31 binary. Then to build the TSP image use:
824
825::
826
827 make PLAT=<platform> SPD=tspd all
828
829An additional boot loader binary file is created in the ``build`` directory:
830
831::
832
833 build/<platform>/<build-type>/bl32.bin
834
835Checking source code style
836~~~~~~~~~~~~~~~~~~~~~~~~~~
837
838When making changes to the source for submission to the project, the source
839must be in compliance with the Linux style guide, and to assist with this check
840the project Makefile contains two targets, which both utilise the
841``checkpatch.pl`` script that ships with the Linux source tree.
842
843To check the entire source tree, you must first download a copy of
844``checkpatch.pl`` (or the full Linux source), set the ``CHECKPATCH`` environment
845variable to point to the script and build the target checkcodebase:
846
847::
848
849 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
850
851To just check the style on the files that differ between your local branch and
852the remote master, use:
853
854::
855
856 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
857
858If you wish to check your patch against something other than the remote master,
859set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
860is set to ``origin/master``.
861
862Building and using the FIP tool
863~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
864
865Firmware Image Package (FIP) is a packaging format used by the Trusted Firmware
866project to package firmware images in a single binary. The number and type of
867images that should be packed in a FIP is platform specific and may include TF
868images and other firmware images required by the platform. For example, most
869platforms require a BL33 image which corresponds to the normal world bootloader
870(e.g. UEFI or U-Boot).
871
872The TF build system provides the make target ``fip`` to create a FIP file for the
873specified platform using the FIP creation tool included in the TF project.
874Examples below show how to build a FIP file for FVP, packaging TF images and a
875BL33 image.
876
877For AArch64:
878
879::
880
881 make PLAT=fvp BL33=<path/to/bl33.bin> fip
882
883For AArch32:
884
885::
886
887 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path/to/bl33.bin> fip
888
889Note that AArch32 support for Normal world boot loader (BL33), like U-boot or
890UEFI, on FVP is not available upstream. Hence custom solutions are required to
891allow Linux boot on FVP. These instructions assume such a custom boot loader
892(BL33) is available.
893
894The resulting FIP may be found in:
895
896::
897
898 build/fvp/<build-type>/fip.bin
899
900For advanced operations on FIP files, it is also possible to independently build
901the tool and create or modify FIPs using this tool. To do this, follow these
902steps:
903
904It is recommended to remove old artifacts before building the tool:
905
906::
907
908 make -C tools/fiptool clean
909
910Build the tool:
911
912::
913
914 make [DEBUG=1] [V=1] fiptool
915
916The tool binary can be located in:
917
918::
919
920 ./tools/fiptool/fiptool
921
922Invoking the tool with ``--help`` will print a help message with all available
923options.
924
925Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
926
927::
928
929 ./tools/fiptool/fiptool create \
930 --tb-fw build/<platform>/<build-type>/bl2.bin \
931 --soc-fw build/<platform>/<build-type>/bl31.bin \
932 fip.bin
933
934Example 2: view the contents of an existing Firmware package:
935
936::
937
938 ./tools/fiptool/fiptool info <path-to>/fip.bin
939
940Example 3: update the entries of an existing Firmware package:
941
942::
943
944 # Change the BL2 from Debug to Release version
945 ./tools/fiptool/fiptool update \
946 --tb-fw build/<platform>/release/bl2.bin \
947 build/<platform>/debug/fip.bin
948
949Example 4: unpack all entries from an existing Firmware package:
950
951::
952
953 # Images will be unpacked to the working directory
954 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
955
956Example 5: remove an entry from an existing Firmware package:
957
958::
959
960 ./tools/fiptool/fiptool remove \
961 --tb-fw build/<platform>/debug/fip.bin
962
963Note that if the destination FIP file exists, the create, update and
964remove operations will automatically overwrite it.
965
966The unpack operation will fail if the images already exist at the
967destination. In that case, use -f or --force to continue.
968
969More information about FIP can be found in the `Firmware Design`_ document.
970
971Migrating from fip\_create to fiptool
972^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
973
974The previous version of fiptool was called fip\_create. A compatibility script
975that emulates the basic functionality of the previous fip\_create is provided.
976However, users are strongly encouraged to migrate to fiptool.
977
978- To create a new FIP file, replace "fip\_create" with "fiptool create".
979- To update a FIP file, replace "fip\_create" with "fiptool update".
980- To dump the contents of a FIP file, replace "fip\_create --dump"
981 with "fiptool info".
982
983Building FIP images with support for Trusted Board Boot
984~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
985
986Trusted Board Boot primarily consists of the following two features:
987
988- Image Authentication, described in `Trusted Board Boot`_, and
989- Firmware Update, described in `Firmware Update`_
990
991The following steps should be followed to build FIP and (optionally) FWU\_FIP
992images with support for these features:
993
994#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
995 modules by checking out a recent version of the `mbed TLS Repository`_. It
996 is important to use a version that is compatible with TF and fixes any
997 known security vulnerabilities. See `mbed TLS Security Center`_ for more
998 information. The latest version of TF is tested with tag ``mbedtls-2.4.2``.
999
1000 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1001 source files the modules depend upon.
1002 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1003 options required to build the mbed TLS sources.
1004
1005 Note that the mbed TLS library is licensed under the Apache version 2.0
1006 license. Using mbed TLS source code will affect the licensing of
1007 Trusted Firmware binaries that are built using this library.
1008
1009#. To build the FIP image, ensure the following command line variables are set
1010 while invoking ``make`` to build Trusted Firmware:
1011
1012 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1013 - ``TRUSTED_BOARD_BOOT=1``
1014 - ``GENERATE_COT=1``
1015
1016 In the case of ARM platforms, the location of the ROTPK hash must also be
1017 specified at build time. Two locations are currently supported (see
1018 ``ARM_ROTPK_LOCATION`` build option):
1019
1020 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1021 root-key storage registers present in the platform. On Juno, this
1022 registers are read-only. On FVP Base and Cortex models, the registers
1023 are read-only, but the value can be specified using the command line
1024 option ``bp.trusted_key_storage.public_key`` when launching the model.
1025 On both Juno and FVP models, the default value corresponds to an
1026 ECDSA-SECP256R1 public key hash, whose private part is not currently
1027 available.
1028
1029 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
1030 in the ARM platform port. The private/public RSA key pair may be
1031 found in ``plat/arm/board/common/rotpk``.
1032
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001033 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
1034 in the ARM platform port. The private/public ECDSA key pair may be
1035 found in ``plat/arm/board/common/rotpk``.
1036
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001037 Example of command line using RSA development keys:
1038
1039 ::
1040
1041 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1042 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1043 ARM_ROTPK_LOCATION=devel_rsa \
1044 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1045 BL33=<path-to>/<bl33_image> \
1046 all fip
1047
1048 The result of this build will be the bl1.bin and the fip.bin binaries. This
1049 FIP will include the certificates corresponding to the Chain of Trust
1050 described in the TBBR-client document. These certificates can also be found
1051 in the output build directory.
1052
1053#. The optional FWU\_FIP contains any additional images to be loaded from
1054 Non-Volatile storage during the `Firmware Update`_ process. To build the
1055 FWU\_FIP, any FWU images required by the platform must be specified on the
1056 command line. On ARM development platforms like Juno, these are:
1057
1058 - NS\_BL2U. The AP non-secure Firmware Updater image.
1059 - SCP\_BL2U. The SCP Firmware Update Configuration image.
1060
1061 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1062 targets using RSA development:
1063
1064 ::
1065
1066 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1067 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1068 ARM_ROTPK_LOCATION=devel_rsa \
1069 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1070 BL33=<path-to>/<bl33_image> \
1071 SCP_BL2=<path-to>/<scp_bl2_image> \
1072 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1073 NS_BL2U=<path-to>/<ns_bl2u_image> \
1074 all fip fwu_fip
1075
1076 Note: The BL2U image will be built by default and added to the FWU\_FIP.
1077 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1078 to the command line above.
1079
1080 Note: Building and installing the non-secure and SCP FWU images (NS\_BL1U,
1081 NS\_BL2U and SCP\_BL2U) is outside the scope of this document.
1082
1083 The result of this build will be bl1.bin, fip.bin and fwu\_fip.bin binaries.
1084 Both the FIP and FWU\_FIP will include the certificates corresponding to the
1085 Chain of Trust described in the TBBR-client document. These certificates
1086 can also be found in the output build directory.
1087
1088Building the Certificate Generation Tool
1089~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1090
1091The ``cert_create`` tool is built as part of the TF build process when the ``fip``
1092make target is specified and TBB is enabled (as described in the previous
1093section), but it can also be built separately with the following command:
1094
1095::
1096
1097 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1098
1099For platforms that do not require their own IDs in certificate files,
1100the generic 'cert\_create' tool can be built with the following command:
1101
1102::
1103
1104 make USE_TBBR_DEFS=1 [DEBUG=1] [V=1] certtool
1105
1106``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1107verbose. The following command should be used to obtain help about the tool:
1108
1109::
1110
1111 ./tools/cert_create/cert_create -h
1112
1113Building a FIP for Juno and FVP
1114-------------------------------
1115
1116This section provides Juno and FVP specific instructions to build Trusted
1117Firmware, obtain the additional required firmware, and pack it all together in
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001118a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001119
David Cunadob2de0992017-06-29 12:01:33 +01001120Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12
1121onwards. Before that release, pre-built binaries are only available for AArch64.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001122
1123Note: follow the full instructions for one platform before switching to a
1124different one. Mixing instructions for different platforms may result in
1125corrupted binaries.
1126
1127#. Clean the working directory
1128
1129 ::
1130
1131 make realclean
1132
1133#. Obtain SCP\_BL2 (Juno) and BL33 (all platforms)
1134
1135 Use the fiptool to extract the SCP\_BL2 and BL33 images from the FIP
1136 package included in the Linaro release:
1137
1138 ::
1139
1140 # Build the fiptool
1141 make [DEBUG=1] [V=1] fiptool
1142
1143 # Unpack firmware images from Linaro FIP
1144 ./tools/fiptool/fiptool unpack \
1145 <path/to/linaro/release>/fip.bin
1146
1147 The unpack operation will result in a set of binary images extracted to the
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001148 current working directory. The SCP\_BL2 image corresponds to
1149 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001150
1151 Note: the fiptool will complain if the images to be unpacked already
1152 exist in the current directory. If that is the case, either delete those
1153 files or use the ``--force`` option to overwrite.
1154
1155 Note for AArch32, the instructions below assume that nt-fw.bin is a custom
1156 Normal world boot loader that supports AArch32.
1157
1158#. Build TF images and create a new FIP for FVP
1159
1160 ::
1161
1162 # AArch64
1163 make PLAT=fvp BL33=nt-fw.bin all fip
1164
1165 # AArch32
1166 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1167
1168#. Build TF images and create a new FIP for Juno
1169
1170 For AArch64:
1171
1172 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1173 as a build parameter.
1174
1175 ::
1176
1177 make PLAT=juno all fip \
1178 BL33=<path-to-juno-oe-uboot>/SOFTWARE/bl33-uboot.bin \
1179 SCP_BL2=<path-to-juno-busybox-uboot>/SOFTWARE/scp_bl2.bin
1180
1181 For AArch32:
1182
1183 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1184 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1185 separately for AArch32.
1186
1187 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1188 to the AArch32 Linaro cross compiler.
1189
1190 ::
1191
1192 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1193
1194 - Build BL32 in AArch32.
1195
1196 ::
1197
1198 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1199 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1200
1201 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1202 must point to the AArch64 Linaro cross compiler.
1203
1204 ::
1205
1206 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1207
1208 - The following parameters should be used to build BL1 and BL2 in AArch64
1209 and point to the BL32 file.
1210
1211 ::
1212
1213 make ARCH=aarch64 PLAT=juno LOAD_IMAGE_V2=1 JUNO_AARCH32_EL3_RUNTIME=1 \
1214 BL33=<path-to-juno32-oe-uboot>/SOFTWARE/bl33-uboot.bin \
Soby Mathewbf169232017-11-14 14:10:10 +00001215 SCP_BL2=<path-to-juno32-oe-uboot>/SOFTWARE/scp_bl2.bin \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001216 BL32=<path-to-bl32>/bl32.bin all fip
1217
1218The resulting BL1 and FIP images may be found in:
1219
1220::
1221
1222 # Juno
1223 ./build/juno/release/bl1.bin
1224 ./build/juno/release/fip.bin
1225
1226 # FVP
1227 ./build/fvp/release/bl1.bin
1228 ./build/fvp/release/fip.bin
1229
Roberto Vargas096f3a02017-10-17 10:19:00 +01001230
1231Booting Firmware Update images
1232-------------------------------------
1233
1234When Firmware Update (FWU) is enabled there are at least 2 new images
1235that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1236FWU FIP.
1237
1238Juno
1239~~~~
1240
1241The new images must be programmed in flash memory by adding
1242an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1243on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1244Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1245programming" for more information. User should ensure these do not
1246overlap with any other entries in the file.
1247
1248::
1249
1250 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1251 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1252 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1253 NOR10LOAD: 00000000 ;Image Load Address
1254 NOR10ENTRY: 00000000 ;Image Entry Point
1255
1256 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1257 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1258 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1259 NOR11LOAD: 00000000 ;Image Load Address
1260
1261The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1262In the same way, the address ns_bl2u_base_address is the value of
1263NS_BL2U_BASE - 0x8000000.
1264
1265FVP
1266~~~
1267
1268The additional fip images must be loaded with:
1269
1270::
1271
1272 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1273 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1274
1275The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1276In the same way, the address ns_bl2u_base_address is the value of
1277NS_BL2U_BASE.
1278
1279
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001280EL3 payloads alternative boot flow
1281----------------------------------
1282
1283On a pre-production system, the ability to execute arbitrary, bare-metal code at
1284the highest exception level is required. It allows full, direct access to the
1285hardware, for example to run silicon soak tests.
1286
1287Although it is possible to implement some baremetal secure firmware from
1288scratch, this is a complex task on some platforms, depending on the level of
1289configuration required to put the system in the expected state.
1290
1291Rather than booting a baremetal application, a possible compromise is to boot
1292``EL3 payloads`` through the Trusted Firmware instead. This is implemented as an
1293alternative boot flow, where a modified BL2 boots an EL3 payload, instead of
1294loading the other BL images and passing control to BL31. It reduces the
1295complexity of developing EL3 baremetal code by:
1296
1297- putting the system into a known architectural state;
1298- taking care of platform secure world initialization;
1299- loading the SCP\_BL2 image if required by the platform.
1300
1301When booting an EL3 payload on ARM standard platforms, the configuration of the
1302TrustZone controller is simplified such that only region 0 is enabled and is
1303configured to permit secure access only. This gives full access to the whole
1304DRAM to the EL3 payload.
1305
1306The system is left in the same state as when entering BL31 in the default boot
1307flow. In particular:
1308
1309- Running in EL3;
1310- Current state is AArch64;
1311- Little-endian data access;
1312- All exceptions disabled;
1313- MMU disabled;
1314- Caches disabled.
1315
1316Booting an EL3 payload
1317~~~~~~~~~~~~~~~~~~~~~~
1318
1319The EL3 payload image is a standalone image and is not part of the FIP. It is
1320not loaded by the Trusted Firmware. Therefore, there are 2 possible scenarios:
1321
1322- The EL3 payload may reside in non-volatile memory (NVM) and execute in
1323 place. In this case, booting it is just a matter of specifying the right
1324 address in NVM through ``EL3_PAYLOAD_BASE`` when building the TF.
1325
1326- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1327 run-time.
1328
1329To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1330used. The infinite loop that it introduces in BL1 stops execution at the right
1331moment for a debugger to take control of the target and load the payload (for
1332example, over JTAG).
1333
1334It is expected that this loading method will work in most cases, as a debugger
1335connection is usually available in a pre-production system. The user is free to
1336use any other platform-specific mechanism to load the EL3 payload, though.
1337
1338Booting an EL3 payload on FVP
1339^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1340
1341The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1342the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1343is undefined on the FVP platform and the FVP platform code doesn't clear it.
1344Therefore, one must modify the way the model is normally invoked in order to
1345clear the mailbox at start-up.
1346
1347One way to do that is to create an 8-byte file containing all zero bytes using
1348the following command:
1349
1350::
1351
1352 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1353
1354and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1355using the following model parameters:
1356
1357::
1358
1359 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1360 --data=mailbox.dat@0x04000000 [Foundation FVP]
1361
1362To provide the model with the EL3 payload image, the following methods may be
1363used:
1364
1365#. If the EL3 payload is able to execute in place, it may be programmed into
1366 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1367 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1368 used for the FIP):
1369
1370 ::
1371
1372 -C bp.flashloader1.fname="/path/to/el3-payload"
1373
1374 On Foundation FVP, there is no flash loader component and the EL3 payload
1375 may be programmed anywhere in flash using method 3 below.
1376
1377#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1378 command may be used to load the EL3 payload ELF image over JTAG:
1379
1380 ::
1381
1382 load /path/to/el3-payload.elf
1383
1384#. The EL3 payload may be pre-loaded in volatile memory using the following
1385 model parameters:
1386
1387 ::
1388
1389 --data cluster0.cpu0="/path/to/el3-payload"@address [Base FVPs]
1390 --data="/path/to/el3-payload"@address [Foundation FVP]
1391
1392 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
1393 used when building the Trusted Firmware.
1394
1395Booting an EL3 payload on Juno
1396^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1397
1398If the EL3 payload is able to execute in place, it may be programmed in flash
1399memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1400on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1401Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1402programming" for more information.
1403
1404Alternatively, the same DS-5 command mentioned in the FVP section above can
1405be used to load the EL3 payload's ELF file over JTAG on Juno.
1406
1407Preloaded BL33 alternative boot flow
1408------------------------------------
1409
1410Some platforms have the ability to preload BL33 into memory instead of relying
1411on Trusted Firmware to load it. This may simplify packaging of the normal world
1412code and improve performance in a development environment. When secure world
1413cold boot is complete, Trusted Firmware simply jumps to a BL33 base address
1414provided at build time.
1415
1416For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
1417used when compiling the Trusted Firmware. For example, the following command
1418will create a FIP without a BL33 and prepare to jump to a BL33 image loaded at
1419address 0x80000000:
1420
1421::
1422
1423 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1424
1425Boot of a preloaded bootwrapped kernel image on Base FVP
1426~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1427
1428The following example uses the AArch64 boot wrapper. This simplifies normal
1429world booting while also making use of TF features. It can be obtained from its
1430repository with:
1431
1432::
1433
1434 git clone git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git
1435
1436After compiling it, an ELF file is generated. It can be loaded with the
1437following command:
1438
1439::
1440
1441 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1442 -C bp.secureflashloader.fname=bl1.bin \
1443 -C bp.flashloader0.fname=fip.bin \
1444 -a cluster0.cpu0=<bootwrapped-kernel.elf> \
1445 --start cluster0.cpu0=0x0
1446
1447The ``-a cluster0.cpu0=<bootwrapped-kernel.elf>`` option loads the ELF file. It
1448also sets the PC register to the ELF entry point address, which is not the
1449desired behaviour, so the ``--start cluster0.cpu0=0x0`` option forces the PC back
1450to 0x0 (the BL1 entry point address) on CPU #0. The ``PRELOADED_BL33_BASE`` define
1451used when compiling the FIP must match the ELF entry point.
1452
1453Boot of a preloaded bootwrapped kernel image on Juno
1454~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1455
1456The procedure to obtain and compile the boot wrapper is very similar to the case
1457of the FVP. The execution must be stopped at the end of bl2\_main(), and the
1458loading method explained above in the EL3 payload boot flow section may be used
1459to load the ELF file over JTAG on Juno.
1460
1461Running the software on FVP
1462---------------------------
1463
1464The latest version of the AArch64 build of ARM Trusted Firmware has been tested
1465on the following ARM FVPs (64-bit host machine only).
1466
Eleanor Bonnicie124dc42017-10-04 15:03:33 +01001467NOTE: Unless otherwise stated, the model version is Version 11.1 Build 11.1.22.
David Cunado124415e2017-06-27 17:31:12 +01001468
1469- ``Foundation_Platform``
Eleanor Bonnicie124dc42017-10-04 15:03:33 +01001470- ``FVP_Base_AEMv8A-AEMv8A`` (Version 8.7, Build 0.8.8702)
David Cunado124415e2017-06-27 17:31:12 +01001471- ``FVP_Base_Cortex-A35x4``
1472- ``FVP_Base_Cortex-A53x4``
1473- ``FVP_Base_Cortex-A57x4-A53x4``
1474- ``FVP_Base_Cortex-A57x4``
1475- ``FVP_Base_Cortex-A72x4-A53x4``
1476- ``FVP_Base_Cortex-A72x4``
1477- ``FVP_Base_Cortex-A73x4-A53x4``
1478- ``FVP_Base_Cortex-A73x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001479
1480The latest version of the AArch32 build of ARM Trusted Firmware has been tested
1481on the following ARM FVPs (64-bit host machine only).
1482
Eleanor Bonnicie124dc42017-10-04 15:03:33 +01001483- ``FVP_Base_AEMv8A-AEMv8A`` (Version 8.7, Build 0.8.8702)
David Cunado124415e2017-06-27 17:31:12 +01001484- ``FVP_Base_Cortex-A32x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001485
1486NOTE: The build numbers quoted above are those reported by launching the FVP
1487with the ``--version`` parameter.
1488
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001489NOTE: Linaro provides a ramdisk image in prebuilt FVP configurations and full
1490file systems that can be downloaded separately. To run an FVP with a virtio
1491file system image an additional FVP configuration option
1492``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1493used.
1494
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001495NOTE: The software will not work on Version 1.0 of the Foundation FVP.
1496The commands below would report an ``unhandled argument`` error in this case.
1497
1498NOTE: FVPs can be launched with ``--cadi-server`` option such that a
1499CADI-compliant debugger (for example, ARM DS-5) can connect to and control its
1500execution.
1501
Eleanor Bonnicie124dc42017-10-04 15:03:33 +01001502NOTE: Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
David Cunado97309462017-07-31 12:24:51 +01001503the internal synchronisation timings changed compared to older versions of the
1504models. The models can be launched with ``-Q 100`` option if they are required
1505to match the run time characteristics of the older versions.
1506
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001507The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
1508downloaded for free from `ARM's website`_.
1509
David Cunado124415e2017-06-27 17:31:12 +01001510The Cortex-A models listed above are also available to download from
1511`ARM's website`_.
1512
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001513Please refer to the FVP documentation for a detailed description of the model
1514parameter options. A brief description of the important ones that affect the ARM
1515Trusted Firmware and normal world software behavior is provided below.
1516
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001517Obtaining the Flattened Device Trees
1518~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1519
1520Depending on the FVP configuration and Linux configuration used, different
1521FDT files are required. FDTs for the Foundation and Base FVPs can be found in
1522the Trusted Firmware source directory under ``fdts/``. The Foundation FVP has a
1523subset of the Base FVP components. For example, the Foundation FVP lacks CLCD
1524and MMC support, and has only one CPU cluster.
1525
1526Note: It is not recommended to use the FDTs built along the kernel because not
1527all FDTs are available from there.
1528
1529- ``fvp-base-gicv2-psci.dtb``
1530
1531 For use with both AEMv8 and Cortex-A57-A53 Base FVPs with
1532 Base memory map configuration.
1533
1534- ``fvp-base-gicv2-psci-aarch32.dtb``
1535
1536 For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state
1537 with Base memory map configuration.
1538
1539- ``fvp-base-gicv3-psci.dtb``
1540
1541 (Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base
1542 memory map configuration and Linux GICv3 support.
1543
1544- ``fvp-base-gicv3-psci-aarch32.dtb``
1545
1546 For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state
1547 with Base memory map configuration and Linux GICv3 support.
1548
1549- ``fvp-foundation-gicv2-psci.dtb``
1550
1551 For use with Foundation FVP with Base memory map configuration.
1552
1553- ``fvp-foundation-gicv3-psci.dtb``
1554
1555 (Default) For use with Foundation FVP with Base memory map configuration
1556 and Linux GICv3 support.
1557
1558Running on the Foundation FVP with reset to BL1 entrypoint
1559~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1560
1561The following ``Foundation_Platform`` parameters should be used to boot Linux with
15624 CPUs using the AArch64 build of ARM Trusted Firmware.
1563
1564::
1565
1566 <path-to>/Foundation_Platform \
1567 --cores=4 \
1568 --secure-memory \
1569 --visualization \
1570 --gicv3 \
1571 --data="<path-to>/<bl1-binary>"@0x0 \
1572 --data="<path-to>/<FIP-binary>"@0x08000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001573 --data="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001574 --data="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001575 --data="<path-to>/<ramdisk-binary>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001576
1577Notes:
1578
1579- BL1 is loaded at the start of the Trusted ROM.
1580- The Firmware Image Package is loaded at the start of NOR FLASH0.
1581- The Linux kernel image and device tree are loaded in DRAM.
1582- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1583 and enable the GICv3 device in the model. Note that without this option,
1584 the Foundation FVP defaults to legacy (Versatile Express) memory map which
1585 is not supported by ARM Trusted Firmware.
1586
1587Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1588~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1589
1590The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1591with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1592
1593::
1594
1595 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1596 -C pctl.startup=0.0.0.0 \
1597 -C bp.secure_memory=1 \
1598 -C bp.tzc_400.diagnostics=1 \
1599 -C cluster0.NUM_CORES=4 \
1600 -C cluster1.NUM_CORES=4 \
1601 -C cache_state_modelled=1 \
1602 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1603 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001604 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001605 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001606 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001607
1608Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1609~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1610
1611The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1612with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
1613
1614::
1615
1616 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1617 -C pctl.startup=0.0.0.0 \
1618 -C bp.secure_memory=1 \
1619 -C bp.tzc_400.diagnostics=1 \
1620 -C cluster0.NUM_CORES=4 \
1621 -C cluster1.NUM_CORES=4 \
1622 -C cache_state_modelled=1 \
1623 -C cluster0.cpu0.CONFIG64=0 \
1624 -C cluster0.cpu1.CONFIG64=0 \
1625 -C cluster0.cpu2.CONFIG64=0 \
1626 -C cluster0.cpu3.CONFIG64=0 \
1627 -C cluster1.cpu0.CONFIG64=0 \
1628 -C cluster1.cpu1.CONFIG64=0 \
1629 -C cluster1.cpu2.CONFIG64=0 \
1630 -C cluster1.cpu3.CONFIG64=0 \
1631 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1632 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001633 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001634 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001635 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001636
1637Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1638~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1639
1640The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
1641boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1642
1643::
1644
1645 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1646 -C pctl.startup=0.0.0.0 \
1647 -C bp.secure_memory=1 \
1648 -C bp.tzc_400.diagnostics=1 \
1649 -C cache_state_modelled=1 \
1650 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1651 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001652 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001653 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001654 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001655
1656Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1657~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1658
1659The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
1660boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
1661
1662::
1663
1664 <path-to>/FVP_Base_Cortex-A32x4 \
1665 -C pctl.startup=0.0.0.0 \
1666 -C bp.secure_memory=1 \
1667 -C bp.tzc_400.diagnostics=1 \
1668 -C cache_state_modelled=1 \
1669 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1670 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001671 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001672 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001673 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001674
1675Running on the AEMv8 Base FVP with reset to BL31 entrypoint
1676~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1677
1678The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1679with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1680
1681::
1682
1683 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1684 -C pctl.startup=0.0.0.0 \
1685 -C bp.secure_memory=1 \
1686 -C bp.tzc_400.diagnostics=1 \
1687 -C cluster0.NUM_CORES=4 \
1688 -C cluster1.NUM_CORES=4 \
1689 -C cache_state_modelled=1 \
Qixiang Xua5f72812017-08-31 11:45:32 +08001690 -C cluster0.cpu0.RVBAR=0x04020000 \
1691 -C cluster0.cpu1.RVBAR=0x04020000 \
1692 -C cluster0.cpu2.RVBAR=0x04020000 \
1693 -C cluster0.cpu3.RVBAR=0x04020000 \
1694 -C cluster1.cpu0.RVBAR=0x04020000 \
1695 -C cluster1.cpu1.RVBAR=0x04020000 \
1696 -C cluster1.cpu2.RVBAR=0x04020000 \
1697 -C cluster1.cpu3.RVBAR=0x04020000 \
1698 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001699 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1700 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001701 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001702 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001703 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001704
1705Notes:
1706
1707- Since a FIP is not loaded when using BL31 as reset entrypoint, the
1708 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
1709 parameter is needed to load the individual bootloader images in memory.
1710 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
1711 Payload.
1712
1713- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
1714 X and Y are the cluster and CPU numbers respectively, is used to set the
1715 reset vector for each core.
1716
1717- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
1718 changing the value of
1719 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
1720 ``BL32_BASE``.
1721
1722Running on the AEMv8 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1723~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1724
1725The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1726with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
1727
1728::
1729
1730 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1731 -C pctl.startup=0.0.0.0 \
1732 -C bp.secure_memory=1 \
1733 -C bp.tzc_400.diagnostics=1 \
1734 -C cluster0.NUM_CORES=4 \
1735 -C cluster1.NUM_CORES=4 \
1736 -C cache_state_modelled=1 \
1737 -C cluster0.cpu0.CONFIG64=0 \
1738 -C cluster0.cpu1.CONFIG64=0 \
1739 -C cluster0.cpu2.CONFIG64=0 \
1740 -C cluster0.cpu3.CONFIG64=0 \
1741 -C cluster1.cpu0.CONFIG64=0 \
1742 -C cluster1.cpu1.CONFIG64=0 \
1743 -C cluster1.cpu2.CONFIG64=0 \
1744 -C cluster1.cpu3.CONFIG64=0 \
1745 -C cluster0.cpu0.RVBAR=0x04001000 \
1746 -C cluster0.cpu1.RVBAR=0x04001000 \
1747 -C cluster0.cpu2.RVBAR=0x04001000 \
1748 -C cluster0.cpu3.RVBAR=0x04001000 \
1749 -C cluster1.cpu0.RVBAR=0x04001000 \
1750 -C cluster1.cpu1.RVBAR=0x04001000 \
1751 -C cluster1.cpu2.RVBAR=0x04001000 \
1752 -C cluster1.cpu3.RVBAR=0x04001000 \
1753 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1754 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001755 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001756 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001757 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001758
1759Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
1760It should match the address programmed into the RVBAR register as well.
1761
1762Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
1763~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1764
1765The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
1766boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
1767
1768::
1769
1770 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1771 -C pctl.startup=0.0.0.0 \
1772 -C bp.secure_memory=1 \
1773 -C bp.tzc_400.diagnostics=1 \
1774 -C cache_state_modelled=1 \
Qixiang Xua5f72812017-08-31 11:45:32 +08001775 -C cluster0.cpu0.RVBARADDR=0x04020000 \
1776 -C cluster0.cpu1.RVBARADDR=0x04020000 \
1777 -C cluster0.cpu2.RVBARADDR=0x04020000 \
1778 -C cluster0.cpu3.RVBARADDR=0x04020000 \
1779 -C cluster1.cpu0.RVBARADDR=0x04020000 \
1780 -C cluster1.cpu1.RVBARADDR=0x04020000 \
1781 -C cluster1.cpu2.RVBARADDR=0x04020000 \
1782 -C cluster1.cpu3.RVBARADDR=0x04020000 \
1783 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001784 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1785 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001786 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001787 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001788 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001789
1790Running on the Cortex-A32 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1791~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1792
1793The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
1794boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
1795
1796::
1797
1798 <path-to>/FVP_Base_Cortex-A32x4 \
1799 -C pctl.startup=0.0.0.0 \
1800 -C bp.secure_memory=1 \
1801 -C bp.tzc_400.diagnostics=1 \
1802 -C cache_state_modelled=1 \
1803 -C cluster0.cpu0.RVBARADDR=0x04001000 \
1804 -C cluster0.cpu1.RVBARADDR=0x04001000 \
1805 -C cluster0.cpu2.RVBARADDR=0x04001000 \
1806 -C cluster0.cpu3.RVBARADDR=0x04001000 \
1807 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1808 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001809 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001810 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001811 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001812
1813Running the software on Juno
1814----------------------------
1815
David Cunadob2de0992017-06-29 12:01:33 +01001816This version of the ARM Trusted Firmware has been tested on variants r0, r1 and
1817r2 of Juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001818
1819To execute the software stack on Juno, the version of the Juno board recovery
1820image indicated in the `Linaro Release Notes`_ must be installed. If you have an
1821earlier version installed or are unsure which version is installed, please
1822re-install the recovery image by following the
1823`Instructions for using Linaro's deliverables on Juno`_.
1824
1825Preparing Trusted Firmware images
1826~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1827
1828After building Trusted Firmware, the files ``bl1.bin`` and ``fip.bin`` need copying
1829to the ``SOFTWARE/`` directory of the Juno SD card.
1830
1831Other Juno software information
1832~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1833
1834Please visit the `ARM Platforms Portal`_ to get support and obtain any other Juno
1835software information. Please also refer to the `Juno Getting Started Guide`_ to
1836get more detailed information about the Juno ARM development platform and how to
1837configure it.
1838
1839Testing SYSTEM SUSPEND on Juno
1840~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1841
1842The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
1843to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
1844on Juno, at the linux shell prompt, issue the following command:
1845
1846::
1847
1848 echo +10 > /sys/class/rtc/rtc0/wakealarm
1849 echo -n mem > /sys/power/state
1850
1851The Juno board should suspend to RAM and then wakeup after 10 seconds due to
1852wakeup interrupt from RTC.
1853
1854--------------
1855
1856*Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.*
1857
David Cunadob2de0992017-06-29 12:01:33 +01001858.. _Linaro: `Linaro Release Notes`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001859.. _Linaro Release: `Linaro Release Notes`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001860.. _Linaro Release Notes: https://community.arm.com/tools/dev-platforms/b/documents/posts/linaro-release-notes-deprecated
David Cunadob2de0992017-06-29 12:01:33 +01001861.. _Linaro Release 17.04: https://community.arm.com/tools/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease17.04
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001862.. _Linaro instructions: https://community.arm.com/dev-platforms/b/documents/posts/instructions-for-using-the-linaro-software-deliverables
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001863.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/b/documents/posts/using-linaros-deliverables-on-juno
1864.. _ARM Platforms Portal: https://community.arm.com/dev-platforms/
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001865.. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01001866.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001867.. _here: psci-lib-integration-guide.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001868.. _Trusted Board Boot: trusted-board-boot.rst
1869.. _Secure-EL1 Payloads and Dispatchers: firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001870.. _Firmware Update: firmware-update.rst
1871.. _Firmware Design: firmware-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001872.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
1873.. _mbed TLS Security Center: https://tls.mbed.org/security
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001874.. _ARM's website: `FVP models`_
1875.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001876.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
David Cunadob2de0992017-06-29 12:01:33 +01001877.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf