developer | e2be2dd | 2021-08-19 15:34:43 +0800 | [diff] [blame] | 1 | /* |
developer | 551250c | 2023-03-01 16:12:46 +0800 | [diff] [blame] | 2 | * Copyright (c) 2021-2023, ARM Limited and Contributors. All rights reserved. |
developer | e2be2dd | 2021-08-19 15:34:43 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef EMI_MPU_H |
| 8 | #define EMI_MPU_H |
| 9 | |
| 10 | #include <platform_def.h> |
| 11 | |
| 12 | #define ENABLE_EMI_MPU_SW_LOCK 1 |
| 13 | |
| 14 | #define EMI_MPU_CTRL (EMI_MPU_BASE + 0x000) |
| 15 | #define EMI_MPU_DBG (EMI_MPU_BASE + 0x004) |
| 16 | #define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100) |
| 17 | #define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200) |
| 18 | #define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region * 4)) |
| 19 | #define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region * 4)) |
| 20 | #define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300) |
| 21 | #define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100)) |
| 22 | #define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800) |
| 23 | #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4)) |
| 24 | #define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900) |
| 25 | #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4)) |
| 26 | #define EMI_MPU_START (0x000) |
| 27 | #define EMI_MPU_END (0x93C) |
| 28 | |
| 29 | #define SUB_EMI_MPU_CTRL (SUB_EMI_MPU_BASE + 0x000) |
| 30 | #define SUB_EMI_MPU_DBG (SUB_EMI_MPU_BASE + 0x004) |
| 31 | #define SUB_EMI_MPU_SA0 (SUB_EMI_MPU_BASE + 0x100) |
| 32 | #define SUB_EMI_MPU_EA0 (SUB_EMI_MPU_BASE + 0x200) |
| 33 | #define SUB_EMI_MPU_SA(region) (SUB_EMI_MPU_SA0 + (region * 4)) |
| 34 | #define SUB_EMI_MPU_EA(region) (SUB_EMI_MPU_EA0 + (region * 4)) |
| 35 | #define SUB_EMI_MPU_APC0 (SUB_EMI_MPU_BASE + 0x300) |
| 36 | #define SUB_EMI_MPU_APC(region, dgroup) (SUB_EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100)) |
| 37 | #define SUB_EMI_MPU_CTRL_D0 (SUB_EMI_MPU_BASE + 0x800) |
| 38 | #define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4)) |
| 39 | #define SUB_EMI_RG_MASK_D0 (SUB_EMI_MPU_BASE + 0x900) |
| 40 | #define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4)) |
| 41 | |
| 42 | #define EMI_MPU_DOMAIN_NUM (16) |
| 43 | #define EMI_MPU_REGION_NUM (32) |
| 44 | #define EMI_MPU_ALIGN_BITS (16) |
| 45 | #define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS) |
| 46 | |
| 47 | #define NO_PROTECTION 0 |
| 48 | #define SEC_RW 1 |
| 49 | #define SEC_RW_NSEC_R 2 |
| 50 | #define SEC_RW_NSEC_W 3 |
| 51 | #define SEC_R_NSEC_R 4 |
| 52 | #define FORBIDDEN 5 |
| 53 | #define SEC_R_NSEC_RW 6 |
| 54 | |
| 55 | #define LOCK 1 |
| 56 | #define UNLOCK 0 |
| 57 | |
| 58 | #define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8) |
| 59 | |
| 60 | #if (EMI_MPU_DGROUP_NUM == 1) |
| 61 | #define SET_ACCESS_PERMISSION(apc_ary, lock, d7, d6, d5, d4, d3, d2, d1, d0) \ |
| 62 | do { \ |
| 63 | apc_ary[1] = 0; \ |
| 64 | apc_ary[0] = \ |
| 65 | (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | \ |
| 66 | (((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) | \ |
| 67 | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \ |
| 68 | (((unsigned int) d1) << 3) | ((unsigned int) d0) | \ |
| 69 | ((unsigned int) lock << 31); \ |
| 70 | } while (0) |
| 71 | #elif (EMI_MPU_DGROUP_NUM == 2) |
| 72 | #define SET_ACCESS_PERMISSION(apc_ary, lock, d15, d14, d13, d12, d11, d10, \ |
| 73 | d9, d8, d7, d6, d5, d4, d3, d2, d1, d0) \ |
| 74 | do { \ |
| 75 | apc_ary[1] = \ |
| 76 | (((unsigned int) d15) << 21) | (((unsigned int) d14) << 18) | \ |
| 77 | (((unsigned int) d13) << 15) | (((unsigned int) d12) << 12) | \ |
| 78 | (((unsigned int) d11) << 9) | (((unsigned int) d10) << 6) | \ |
| 79 | (((unsigned int) d9) << 3) | ((unsigned int) d8); \ |
| 80 | apc_ary[0] = \ |
| 81 | (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | \ |
| 82 | (((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) | \ |
| 83 | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \ |
| 84 | (((unsigned int) d1) << 3) | ((unsigned int) d0) | \ |
| 85 | ((unsigned int) lock << 31); \ |
| 86 | } while (0) |
| 87 | #endif |
| 88 | |
| 89 | struct emi_region_info_t { |
| 90 | unsigned long long start; |
| 91 | unsigned long long end; |
| 92 | unsigned int region; |
| 93 | unsigned int apc[EMI_MPU_DGROUP_NUM]; |
| 94 | }; |
| 95 | |
developer | 551250c | 2023-03-01 16:12:46 +0800 | [diff] [blame] | 96 | enum MPU_REQ_ORIGIN_ZONE_ID { |
| 97 | MPU_REQ_ORIGIN_TEE_ZONE_SVP = 0, |
| 98 | MPU_REQ_ORIGIN_TEE_ZONE_TUI = 1, |
| 99 | MPU_REQ_ORIGIN_TEE_ZONE_WFD = 2, |
| 100 | MPU_REQ_ORIGIN_TEE_ZONE_MAX = 3, |
| 101 | MPU_REQ_ORIGIN_ZONE_INVALID = 0x7FFFFFFF, |
| 102 | }; |
| 103 | |
developer | e2be2dd | 2021-08-19 15:34:43 +0800 | [diff] [blame] | 104 | void emi_mpu_init(void); |
developer | 551250c | 2023-03-01 16:12:46 +0800 | [diff] [blame] | 105 | int32_t emi_mpu_sip_handler(uint64_t encoded_addr, uint64_t zone_size, uint64_t zone_info); |
developer | e2be2dd | 2021-08-19 15:34:43 +0800 | [diff] [blame] | 106 | |
| 107 | #endif |